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From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
To: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Zong Li <zong.li@sifive.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <Atish.Patra@rivosinc.com>,
	Christoph Hellwig <hch@lst.de>,
	Andrey Ryabinin <ryabinin.a.a@gmail.com>,
	Alexander Potapenko <glider@google.com>,
	Andrey Konovalov <andreyknvl@gmail.com>,
	Dmitry Vyukov <dvyukov@google.com>,
	Ard Biesheuvel <ardb@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Kees Cook <keescook@chromium.org>,
	Guo Ren <guoren@linux.alibaba.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Mayuresh Chitale <mchitale@ventanamicro.com>,
	panqinglin2020@iscas.ac.cn, linux-doc@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kasan-dev@googlegroups.com, linux-efi@vger.kernel.org,
	linux-arch@vger.kernel.org
Cc: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Subject: [PATCH v3 13/13] riscv: Allow user to downgrade to sv39 when hw supports sv48 if !KASAN
Date: Mon,  6 Dec 2021 11:46:57 +0100	[thread overview]
Message-ID: <20211206104657.433304-14-alexandre.ghiti@canonical.com> (raw)
In-Reply-To: <20211206104657.433304-1-alexandre.ghiti@canonical.com>

This is made possible by using the mmu-type property of the cpu node of
the device tree.

By default, the kernel will boot with 4-level page table if the hw supports
it but it can be interesting for the user to select 3-level page table as
it is less memory consuming and faster since it requires less memory
accesses in case of a TLB miss.

This functionality requires that kasan is disabled since calling the fdt
functions that are kasan instrumented with the MMU off can't work.

Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
---
 arch/riscv/mm/init.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 28de6ea0a720..299b5a44f902 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -633,10 +633,38 @@ static void __init disable_pgtable_l4(void)
  * then read SATP to see if the configuration was taken into account
  * meaning sv48 is supported.
  */
-static __init void set_satp_mode(void)
+static __init void set_satp_mode(uintptr_t dtb_pa)
 {
 	u64 identity_satp, hw_satp;
 	uintptr_t set_satp_mode_pmd;
+#ifndef CONFIG_KASAN
+	/*
+	 * The below fdt functions are kasan instrumented, since at this point
+	 * there is no mapping for the kasan shadow memory, this can't be used
+	 * when kasan is enabled otherwise it traps.
+	 */
+	int cpus_node;
+
+	/* Check if the user asked for sv39 explicitly in the device tree */
+	cpus_node = fdt_path_offset((void *)dtb_pa, "/cpus");
+	if (cpus_node >= 0) {
+		int node;
+
+		fdt_for_each_subnode(node, (void *)dtb_pa, cpus_node) {
+			const char *mmu_type = fdt_getprop((void *)dtb_pa, node,
+					"mmu-type", NULL);
+			if (!mmu_type)
+				continue;
+
+			if (!strcmp(mmu_type, "riscv,sv39")) {
+				disable_pgtable_l4();
+				return;
+			}
+
+			break;
+		}
+	}
+#endif
 
 	set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK;
 	create_pgd_mapping(early_pg_dir,
@@ -838,7 +866,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 #endif
 
 #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL)
-	set_satp_mode();
+	set_satp_mode(dtb_pa);
 #endif
 
 	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
-- 
2.32.0


  parent reply	other threads:[~2021-12-06 11:00 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-06 10:46 [PATCH v3 00/13] Introduce sv48 support without relocatable kernel Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 01/13] riscv: Move KASAN mapping next to the kernel mapping Alexandre Ghiti
2021-12-06 16:18   ` Jisheng Zhang
2021-12-06 10:46 ` [PATCH v3 02/13] riscv: Split early kasan mapping to prepare sv48 introduction Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 03/13] riscv: Introduce functions to switch pt_ops Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 04/13] riscv: Allow to dynamically define VA_BITS Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 05/13] riscv: Get rid of MAXPHYSMEM configs Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 06/13] asm-generic: Prepare for riscv use of pud_alloc_one and pud_free Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 07/13] riscv: Implement sv48 support Alexandre Ghiti
2021-12-06 11:05   ` Alexandre ghiti
2021-12-09  4:32     ` 潘庆霖
2021-12-26  8:59   ` Jisheng Zhang
2022-01-04 12:44     ` Alexandre Ghiti
2021-12-29  3:42   ` Guo Ren
2022-01-04 12:42     ` Alexandre Ghiti
2022-04-26  5:57   ` Nick Kossifidis
2021-12-06 10:46 ` [PATCH v3 08/13] riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 09/13] riscv: Explicit comment about user virtual address space size Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 10/13] riscv: Improve virtual kernel memory layout dump Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 11/13] Documentation: riscv: Add sv48 description to VM layout Alexandre Ghiti
2021-12-06 10:46 ` [PATCH v3 12/13] riscv: Initialize thread pointer before calling C functions Alexandre Ghiti
2021-12-20  9:11   ` Guo Ren
2021-12-20  9:17     ` Ard Biesheuvel
2021-12-20 13:40       ` Guo Ren
2022-01-10  8:03   ` Alexandre ghiti
2021-12-06 10:46 ` Alexandre Ghiti [this message]
2021-12-06 11:08 ` [PATCH v3 00/13] Introduce sv48 support without relocatable kernel Alexandre ghiti
2022-01-20  4:18 ` Palmer Dabbelt
2022-01-20  7:30   ` Alexandre Ghiti
2022-01-20 10:05     ` Alexandre Ghiti
2022-02-18 10:45       ` Alexandre Ghiti
2022-04-01 12:56         ` Alexandre Ghiti
2022-04-23  1:50           ` Palmer Dabbelt
2022-06-02  3:43             ` Palmer Dabbelt

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