From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38BF3C433DF for ; Sun, 7 Jun 2020 17:24:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D78020663 for ; Sun, 7 Jun 2020 17:24:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=gmx.net header.i=@gmx.net header.b="FdvCe4vS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726830AbgFGRYz (ORCPT ); Sun, 7 Jun 2020 13:24:55 -0400 Received: from mout.gmx.net ([212.227.15.18]:38901 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726823AbgFGRYy (ORCPT ); Sun, 7 Jun 2020 13:24:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1591550672; bh=prmDdHGznxEpRFD6qAZXytWIpuhGL6ohzpD4KpRxtZs=; h=X-UI-Sender-Class:Subject:To:Cc:References:From:Date:In-Reply-To; b=FdvCe4vSfuo0ppSsAdk5B8HC5Frbwgabvyv/fN3MZkE0kuYLmgxw72SoYLa6CbBFY t5st3wyVj/Jzmtz8GdcEi4eL+wRC1F9mooJ7Ld/lNbAM4qg/qew1J7wR5aQKbKFOOk ZgZ0f8RDZpZGUW93a0iWOjwHmL/M2DXKGsgdA+MQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from [192.168.123.51] ([88.152.145.75]) by mail.gmx.com (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MFKKh-1jjtur1GKf-00FoF0; Sun, 07 Jun 2020 19:24:32 +0200 Subject: Re: [PATCH v2 1/2] efi/arm: decompressor: deal with HYP mode boot gracefully To: Ard Biesheuvel , linux-efi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, maz@kernel.org, linux@armlinux.org.uk, Chen-Yu Tsai References: <20200607135834.898294-1-ardb@kernel.org> <20200607135834.898294-2-ardb@kernel.org> From: Heinrich Schuchardt Autocrypt: addr=xypron.glpk@gmx.de; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.1 MIME-Version: 1.0 In-Reply-To: <20200607135834.898294-2-ardb@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:Yl00i5pEvP9g3dZ8sbtpZupknrHAgj6gLzFxvMC/IUpoSRBNcnu PVqj+0BmpN+X38nHN8AYdu/x4X2WmJBlTNrfJvwlyfISCeDuQcRY0xRtP980hW2gGzPEwJv 0EqmFOeoxwnC6WrlF8B114szrVcat2M3Yo/t30MV1V4mLrp7UB/jrEr1QrlkdBBdvpBQ7Bg PUI+D6ADnkBq0x/vuis4Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:uFC9UluCpPA=:H3z5/XeJ/k+t/1WRyoFuSQ csA2qDu1QdkNIB/5L3bIvPFT72C6jTJcODCGuQf5e3eZGbb0Y5HP8u/xsGtvrcYC+zuke3P45 vBlN2EIbH18qY0ulEfBU4QN6rWct6xHCmTz30AtR0EgXeQZV5tniG1SAtbXyqXQTr2ptScTni I+7CNdJH9Z4ByOPWbDC0/RfqnZB8aLZTwACVw6cTZZDqDoCcjD4Lh4bHAgmjabL98XTNgpnXo sZ7VkrUtS8xrmXmCktSn1UAEEkIvaXm8rU7XUCJUIukocypGiG1927UnbtDmDV2sF1708Vo1q Uxef8DhjrNFHBG211m/ZYpKXNn7FyRtiDKXEelEzvLYE6OPs7SonwMdwsZbiOrG2ON+0LzcYI FGcbEuehWWbzKpGlshYXuXBavy0N9gBZ0wHrznfFUjMiWg4kOAr/DGiu198HIIe4dfIpdtmd1 J7NoOO5DC58rJOjhgUa8rOq2PHFI7+w3q/PM4FhgL3f8ZMx2oHVfeh7BQVssA33YageYrCEU0 ATxQMF8Aaemo6W7b+VEHClfP/BcvK2ff84SSQYxsvS6RE+rg7r0AIKWDPoZmHDCt0s2B03Qee UKZ05IYG6oe06f9RFgYowxhHh41oIGUonTc8ixmguqNdKIbYT1gcKupiZQ3KSNAOx+y5bdrnC Gh6TyTP5JLrUf4f/6Ql6yJQ9CgEpXZBpuI5XyotT/0I/wouqO5qPzOyFeFUYOyNLV5R+IgG1O PDgCPAFJCO1mAotwJmTizeFKCMdcWH5/BhDoE+YJCHX2KXnwGekveJSAfEPIxfS3uyY1DApIv XU6DYXfiCy06/i1WqEQHCPR/YEPCfoDIv23BpLRJdAaQWkslyey+aAytizB8EGg3x/jr/8ExE rrvFQvIDdiJRR5pBZ5Jz/Qlj1nF1/n+eFBjr7HhM+HOigX1ansX5+rsvlTsVh6LtLtRoAUZkB J04NGeMtdmvNCQuf8Bx8mCq6+6RPOwGAMxfLOAhDxzv1VP3jMnIj9/ncKjOm3MRsup3IjX7mU v0MZLUcE0h9fyVeqWXnziRpdeFJoQtgMWaUHxLpb/jsqhrLHa7phOaJAiCUXEGgutLWSyIevj 4q1ehhX76G8eYlacFITWGJggU/kVW29EJIKVECf4oEdWZNlqySZBljou2uaLmbrjX0X9Yd/kw G1uCZ0PuCg3SAPf63nPQzdOJijmGKcjeVaKZOSPfPM5SCPAmaNDCVKDJv4zeir+v9cw4vrNHI 4mjUo4sgaiuzUNSvR Sender: linux-efi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org On 6/7/20 3:58 PM, Ard Biesheuvel wrote: > EFI on ARM only supports short descriptors, and given that it mandates > that the MMU and caches are on, it is implied that booting in HYP mode > is not supported. > > However, implementations of EFI exist (i.e., U-Boot) that ignore this > requirement, which is not entirely unreasonable, given that it makes > HYP mode inaccessible to the operating system. > > So let's make sure that we can deal with this condition gracefully. > We already tolerate booting the EFI stub with the caches off (even > though this violates the EFI spec as well), and so we should deal > with HYP mode boot with MMU and caches either on or off. > > - When the MMU and caches are on, we can ignore the HYP stub altogether, > since we can carry on executing at HYP. We do need to ensure that we > disable the MMU at HYP before entering the kernel proper. > > - When the MMU and caches are off, we have to drop to SVC mode so that > we can set up the page tables using short descriptors. In this case, > we need to install the HYP stub as usual, so that we can return to HYP > mode before handing over to the kernel proper. To me it is still unclear why you need this patch. Please, describe the problem this patch fixes. Is there any device that you cannot boot without the patch? > > Signed-off-by: Ard Biesheuvel > --- > arch/arm/boot/compressed/head.S | 61 ++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/= head.S > index c79db44ba128..3476e85c31e7 100644 > --- a/arch/arm/boot/compressed/head.S > +++ b/arch/arm/boot/compressed/head.S > @@ -1410,7 +1410,11 @@ memdump: mov r12, r0 > __hyp_reentry_vectors: > W(b) . @ reset > W(b) . @ undef > +#ifdef CONFIG_EFI_STUB > + W(b) __enter_kernel_from_hyp @ hvc from HYP > +#else > W(b) . @ svc > +#endif > W(b) . @ pabort > W(b) . @ dabort > W(b) __enter_kernel @ hyp > @@ -1429,14 +1433,71 @@ __enter_kernel: > reloc_code_end: > > #ifdef CONFIG_EFI_STUB > +__enter_kernel_from_hyp: > + mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR > + bic r0, r0, #0x5 @ disable MMU and caches > + mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR > + isb > + b __enter_kernel > + > ENTRY(efi_enter_kernel) > mov r4, r0 @ preserve image base > mov r8, r1 @ preserve DT pointer > > + ARM( adrl r0, call_cache_fn ) > + THUMB( adr r0, call_cache_fn ) > + adr r1, 0f @ clean the region of code we > + bl cache_clean_flush @ may run with the MMU off > + > +#ifdef CONFIG_ARM_VIRT_EXT > + @ > + @ The EFI spec does not support booting on ARM in HYP mode, > + @ since it mandates that the MMU and caches are on, with all > + @ 32-bit addressable DRAM mapped 1:1 using short descriptors. > + @ > + @ While the EDK2 reference implementation adheres to this, > + @ U-Boot might decide to enter the EFI stub in HYP mode > + @ anyway, with the MMU and caches either on or off. > + @ > + mrs r0, cpsr @ get the current mode > + msr spsr_cxsf, r0 @ record boot mode > + and r0, r0, #MODE_MASK @ are we running in HYP mode? > + cmp r0, #HYP_MODE > + bne .Lefi_svc > + > + mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR > + tst r1, #0x1 @ MMU enabled at HYP? > + beq 1f > + > + @ > + @ When running in HYP mode with the caches on, we're better > + @ off just carrying on using the cached 1:1 mapping that the > + @ firmware provided. Set up the HYP vectors so HVC instructions > + @ issued from HYP mode take us to the correct handler code. We > + @ will disable the MMU before jumping to the kernel proper. > + @ > + adr r0, __hyp_reentry_vectors > + mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR) > + isb > + b .Lefi_hyp > + > + @ > + @ When running in HYP mode with the caches off, we need to drop > + @ into SVC mode now, and let the decompressor set up its cached > + @ 1:1 mapping as usual. > + @ > +1: mov r9, r4 @ preserve image base > + bl __hyp_stub_install @ install HYP stub vectors > + safe_svcmode_maskall r1 @ drop to SVC mode Are you returning to HYP mode somewhere? What is the effect on PSCI? The Allwinner/Sunxi boards must be booted in HYP mode to have PSCI according to https://linux-sunxi.org/PSCI Did you test that you still can reboot those boards? Cc: Chen-Yu Tsai (maintainer ARM/Allwinner sunXi SoC support) Best regards Heinrich > + orr r4, r9, #1 @ restore image base and set LSB > + b .Lefi_hyp > +.Lefi_svc: > +#endif > mrc p15, 0, r0, c1, c0, 0 @ read SCTLR > tst r0, #0x1 @ MMU enabled? > orreq r4, r4, #1 @ set LSB if not > > +.Lefi_hyp: > mov r0, r8 @ DT start > add r1, r8, r2 @ DT end > bl cache_clean_flush >