From: Russ Weight <russell.h.weight@intel.com> To: mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, Russ Weight <russell.h.weight@intel.com> Subject: [PATCH v7 6/6] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func Date: Tue, 5 Jan 2021 15:08:55 -0800 [thread overview] Message-ID: <20210105230855.15019-7-russell.h.weight@intel.com> (raw) In-Reply-To: <20210105230855.15019-1-russell.h.weight@intel.com> Extend the MAX10 BMC Secure Update driver to include a function that returns 64 bits of additional HW specific data for errors that require additional information. This callback function enables the hw_errinfo sysfs node in the Intel Security Manager class driver. Signed-off-by: Russ Weight <russell.h.weight@intel.com> --- v7: - No change v6: - Initialized auth_result and doorbell to HW_ERRINFO_POISON in m10bmc_sec_hw_errinfo() and removed unnecessary if statements. v5: - No change v4: - No change v3: - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update driver" v2: - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to ensure that corresponding bits are set to 1 if we are unable to read the doorbell or auth_result registers. - Added m10bmc_ prefix to functions in m10bmc_iops structure drivers/fpga/intel-m10-bmc-secure.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c index a290fcc4df4a..3a049c98cf43 100644 --- a/drivers/fpga/intel-m10-bmc-secure.c +++ b/drivers/fpga/intel-m10-bmc-secure.c @@ -476,11 +476,33 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr) return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE; } +#define HW_ERRINFO_POISON GENMASK(31, 0) +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr) +{ + struct m10bmc_sec *sec = smgr->priv; + u32 auth_result = HW_ERRINFO_POISON; + u32 doorbell = HW_ERRINFO_POISON; + + switch (smgr->err_code) { + case FPGA_SEC_ERR_HW_ERROR: + case FPGA_SEC_ERR_TIMEOUT: + case FPGA_SEC_ERR_BUSY: + case FPGA_SEC_ERR_WEAROUT: + m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result); + + return (u64)doorbell << 32 | (u64)auth_result; + default: + return 0; + } +} + static const struct fpga_sec_mgr_ops m10bmc_sops = { .prepare = m10bmc_sec_prepare, .write_blk = m10bmc_sec_write_blk, .poll_complete = m10bmc_sec_poll_complete, .cancel = m10bmc_sec_cancel, + .get_hw_errinfo = m10bmc_sec_hw_errinfo, }; static int m10bmc_secure_probe(struct platform_device *pdev) -- 2.25.1
next prev parent reply other threads:[~2021-01-05 23:10 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-05 23:08 [PATCH v7 0/6] Intel MAX10 BMC Secure Update Driver Russ Weight 2021-01-05 23:08 ` [PATCH v7 1/6] mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates Russ Weight 2021-01-05 23:08 ` [PATCH v7 2/6] fpga: m10bmc-sec: create max10 bmc secure update driver Russ Weight 2021-01-05 23:08 ` [PATCH v7 3/6] fpga: m10bmc-sec: expose max10 flash update count Russ Weight 2021-01-05 23:08 ` [PATCH v7 4/6] fpga: m10bmc-sec: expose max10 canceled keys in sysfs Russ Weight 2021-01-05 23:08 ` [PATCH v7 5/6] fpga: m10bmc-sec: add max10 secure update functions Russ Weight 2021-01-05 23:08 ` Russ Weight [this message] 2021-01-19 20:49 ` [PATCH v7 0/6] Intel MAX10 BMC Secure Update Driver Tom Rix 2021-01-21 20:06 ` Russ Weight
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