[PATCH v8 0/5]Add Bitstream configuration support for Versal

[PATCH v8 0/5]Add Bitstream configuration support for Versal

[Nava kishore Manne]

This series Adds FPGA manager driver support for Xilinx Versal SoC.
it uses the firmware interface to configure the programmable logic.

Changes for v4:
                -Rebase the patch series on linux-next.
                https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

Changes for v5:
                -Updated binding doc's.

Changes for v6:
                -Updated firmware binding doc.

Changes for v7:
               -Updated versal-fpga.c driver to remove unwated priv
                struct dependency.

Changes for v8:
                -Removed xlnx,zynqmp-firmware.txt and fixed some minor issues
                 in xlnx,zynqmp-firmware.yaml file as suggested by rob.


Appana Durga Kedareswara rao (1):
  dt-bindings: fpga: Add binding doc for versal fpga manager

Nava kishore Manne (4):
  drivers: firmware: Add PDI load API support
  dt-bindings: firmware: Add bindings for xilinx firmware
  dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file
  fpga: versal-fpga: Add versal fpga manager driver

 .../firmware/xilinx/xlnx,zynqmp-firmware.txt  | 44 ---------
 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 89 +++++++++++++++++
 .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++
 drivers/firmware/xilinx/zynqmp.c              | 17 ++++
 drivers/fpga/Kconfig                          |  9 ++
 drivers/fpga/Makefile                         |  1 +
 drivers/fpga/versal-fpga.c                    | 96 +++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          | 10 ++
 8 files changed, 255 insertions(+), 44 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
 create mode 100644 drivers/fpga/versal-fpga.c

-- 
2.17.1

[PATCH v8 1/5] drivers: firmware: Add PDI load API support

[Nava kishore Manne]

This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
              -Updated API Doc and commit msg.
               No functional changes.

Changes for v3:
              -None.

Changes for v4:
              -Rebased the changes on linux-next.
               No functional changes

Changes for v5:
              -None.

Changes for v6:
              -None.

Changes for v7:
              -None.

Changes for v8:
               -None.

 drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 15b138326ecc..2db571da9ad8 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
 
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src:       Source device where PDI is located
+ * @address:   PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+				   lower_32_bits(address),
+				   upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
 /**
  * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
  * AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9d1a5c175065..56b426fe020c 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
 #define	ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
 #define	ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
 
+/* Loader commands */
+#define PM_LOAD_PDI	0x701
+#define PDI_SRC_DDR	0xF
+
 /*
  * Firmware FPGA Manager flags
  * XILINX_ZYNQMP_PM_FPGA_FULL:	FPGA full reconfiguration
@@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 				 u32 *value);
 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 				 u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 #else
 static inline int zynqmp_pm_get_api_version(u32 *version)
 {
@@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 {
 	return -ENODEV;
 }
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.17.1

Re: [PATCH v8 1/5] drivers: firmware: Add PDI load API support

[Tom Rix]

On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> This patch adds load PDI API support to enable full/partial PDI loading
> from linux. Programmable Device Image (PDI) is combination of headers,
> images and bitstream files to be loaded.
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> Changes for v2:
>                -Updated API Doc and commit msg.
>                 No functional changes.
>
> Changes for v3:
>                -None.
>
> Changes for v4:
>                -Rebased the changes on linux-next.
>                 No functional changes
>
> Changes for v5:
>                -None.
>
> Changes for v6:
>                -None.
>
> Changes for v7:
>                -None.
>
> Changes for v8:
>                 -None.
>
>   drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
>   include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
>   2 files changed, 27 insertions(+)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 15b138326ecc..2db571da9ad8 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
>   }
>   EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
>   
> +/**
> + * zynqmp_pm_load_pdi - Load and process PDI
> + * @src:       Source device where PDI is located
> + * @address:   PDI src address
> + *
> + * This function provides support to load PDI from linux
> + *
> + * Return: Returns status, either success or error+reason
> + */
> +int zynqmp_pm_load_pdi(const u32 src, const u64 address)
> +{
> +	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
> +				   lower_32_bits(address),
> +				   upper_32_bits(address), 0, NULL);
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
> +
>   /**
>    * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
>    * AES-GCM core.
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 9d1a5c175065..56b426fe020c 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -52,6 +52,10 @@
>   #define	ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
>   #define	ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
>   
> +/* Loader commands */
> +#define PM_LOAD_PDI	0x701
This should be defined in enum pm_api_id
> +#define PDI_SRC_DDR	0xF

This is only used by versal_fpga_ops_write(), consider moving the 
#define to versal-fpga.c

Tom

> +
>   /*
>    * Firmware FPGA Manager flags
>    * XILINX_ZYNQMP_PM_FPGA_FULL:	FPGA full reconfiguration
> @@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
>   				 u32 *value);
>   int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
>   				 u32 value);
> +int zynqmp_pm_load_pdi(const u32 src, const u64 address);
>   #else
>   static inline int zynqmp_pm_get_api_version(u32 *version)
>   {
> @@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
>   {
>   	return -ENODEV;
>   }
> +
> +static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
> +{
> +	return -ENODEV;
> +}
>   #endif
>   
>   #endif /* __FIRMWARE_ZYNQMP_H__ */

RE: [PATCH v8 1/5] drivers: firmware: Add PDI load API support

[Nava kishore Manne]

Hi Tom,

	Please fix my response inline.

> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Wednesday, July 7, 2021 2:34 AM
> To: Nava kishore Manne <navam@xilinx.com>; robh+dt@kernel.org; Michal
> Simek <michals@xilinx.com>; mdf@kernel.org; arnd@arndb.de; Rajan Vaja
> <RAJANV@xilinx.com>; gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <ravipate@xlnx.xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v8 1/5] drivers: firmware: Add PDI load API support
> 
> 
> On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> > This patch adds load PDI API support to enable full/partial PDI
> > loading from linux. Programmable Device Image (PDI) is combination of
> > headers, images and bitstream files to be loaded.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > ---
> > Changes for v2:
> >                -Updated API Doc and commit msg.
> >                 No functional changes.
> >
> > Changes for v3:
> >                -None.
> >
> > Changes for v4:
> >                -Rebased the changes on linux-next.
> >                 No functional changes
> >
> > Changes for v5:
> >                -None.
> >
> > Changes for v6:
> >                -None.
> >
> > Changes for v7:
> >                -None.
> >
> > Changes for v8:
> >                 -None.
> >
> >   drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
> >   include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
> >   2 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/firmware/xilinx/zynqmp.c
> > b/drivers/firmware/xilinx/zynqmp.c
> > index 15b138326ecc..2db571da9ad8 100644
> > --- a/drivers/firmware/xilinx/zynqmp.c
> > +++ b/drivers/firmware/xilinx/zynqmp.c
> > @@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32
> node, const u32 capabilities,
> >   }
> >   EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
> >
> > +/**
> > + * zynqmp_pm_load_pdi - Load and process PDI
> > + * @src:       Source device where PDI is located
> > + * @address:   PDI src address
> > + *
> > + * This function provides support to load PDI from linux
> > + *
> > + * Return: Returns status, either success or error+reason  */ int
> > +zynqmp_pm_load_pdi(const u32 src, const u64 address) {
> > +	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
> > +				   lower_32_bits(address),
> > +				   upper_32_bits(address), 0, NULL); }
> > +EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
> > +
> >   /**
> >    * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data
> using
> >    * AES-GCM core.
> > diff --git a/include/linux/firmware/xlnx-zynqmp.h
> > b/include/linux/firmware/xlnx-zynqmp.h
> > index 9d1a5c175065..56b426fe020c 100644
> > --- a/include/linux/firmware/xlnx-zynqmp.h
> > +++ b/include/linux/firmware/xlnx-zynqmp.h
> > @@ -52,6 +52,10 @@
> >   #define	ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
> >   #define	ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
> >
> > +/* Loader commands */
> > +#define PM_LOAD_PDI	0x701
> This should be defined in enum pm_api_id
> > +#define PDI_SRC_DDR	0xF
> 
> This is only used by versal_fpga_ops_write(), consider moving the #define to
> versal-fpga.c
> 

Yes, currently only versal_fpga_write() is using this #define but it’s a generic thing for Versal platform
That’s why we placed it here.

Regards,
Navakishore. 

[PATCH v8 2/5] dt-bindings: fpga: Add binding doc for versal fpga manager

[Nava kishore Manne]

From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>

This patch adds binding doc for versal fpga manager driver.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v2:
              -Fixed file format and syntax issues.

Changes for v3:
              -Removed unwated extra spaces.

Changes for v4:
              -Rebased the changes on linux-next.
               No functional changes

Changes for v5:
              -Updated fpga node name to versal_fpga.

Changes for v6:
              -None.

Changes for v7:
              -None.

Changes for v8:
              -None.

 .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index 000000000000..ac6a207278d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description: |
+  Device Tree Versal FPGA bindings for the Versal SoC, controlled
+  using firmware interface.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,versal-fpga
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    versal_fpga: versal_fpga {
+         compatible = "xlnx,versal-fpga";
+    };
+
+...
-- 
2.17.1

[PATCH v8 3/5] dt-bindings: firmware: Add bindings for xilinx firmware

[Nava kishore Manne]

Add documentation to describe Xilinx firmware driver bindings.
Firmware driver provides an interface to firmware APIs.
Interface APIs can be used by any driver to communicate
to Platform Management Unit.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v4:
              -Added new yaml file for xilinx firmware
               as suggested by Rob.

Changes for v5:
              -Fixed some minor issues and updated the fpga node name to versal_fpga.

Changes for v6:
              -Added AES and Clk nodes as a sub nodes to the firmware node.

Changes for v7:
              -Fixed child nodes format ssues.

Changes for v8:
                -Fixed some minor issues as suggested by rob.

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 89 +++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
new file mode 100644
index 000000000000..f14f7b454f07
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx firmware driver
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description: The zynqmp-firmware node describes the interface to platform
+  firmware. ZynqMP has an interface to communicate with secure firmware.
+  Firmware driver provides an interface to firmware APIs. Interface APIs
+  can be used by any driver to communicate to PMUFW(Platform Management Unit).
+  These requests include clock management, pin control, device control,
+  power management service, FPGA service and other platform management
+  services.
+
+properties:
+  compatible:
+    oneOf:
+      - description: For implementations complying for Zynq Ultrascale+ MPSoC.
+        const: xlnx,zynqmp-firmware
+
+      - description: For implementations complying for Versal.
+        const: xlnx,versal-firmware
+
+  method:
+    description: |
+                 The method of calling the PM-API firmware layer.
+                 Permitted values are.
+                 - "smc" : SMC #0, following the SMCCC
+                 - "hvc" : HVC #0, following the SMCCC
+
+    $ref: /schemas/types.yaml#/definitions/string-array
+    enum:
+      - smc
+      - hvc
+
+  versal_fpga:
+    $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
+    description: Compatible of the FPGA device.
+    type: object
+
+  zynqmp-aes:
+    $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
+    description: The ZynqMP AES-GCM hardened cryptographic accelerator is
+      used to encrypt or decrypt the data with provided key and initialization
+      vector.
+    type: object
+
+  clock-controller:
+    $ref: /schemas/clock/xlnx,versal-clk.yaml#
+    description: The clock controller is a hardware block of Xilinx versal
+      clock tree. It reads required input clock frequencies from the devicetree
+      and acts as clock provider for all clock consumers of PS clocks.list of
+      clock specifiers which are external input clocks to the given clock
+      controller.
+    type: object
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    versal-firmware {
+      compatible = "xlnx,versal-firmware";
+      method = "smc";
+
+      versal_fpga: versal_fpga {
+        compatible = "xlnx,versal-fpga";
+      };
+
+      xlnx_aes: zynqmp-aes {
+        compatible = "xlnx,zynqmp-aes";
+      };
+
+      versal_clk: clock-controller {
+        #clock-cells = <1>;
+        compatible = "xlnx,versal-clk";
+        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
+        clock-names = "ref", "alt_ref", "pl_alt_ref";
+      };
+    };
+
+...
-- 
2.17.1

Re: [PATCH v8 3/5] dt-bindings: firmware: Add bindings for xilinx firmware

[Rob Herring]

On Sat, 26 Jun 2021 21:22:46 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx firmware driver bindings.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate
> to Platform Management Unit.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v4:
>               -Added new yaml file for xilinx firmware
>                as suggested by Rob.
> 
> Changes for v5:
>               -Fixed some minor issues and updated the fpga node name to versal_fpga.
> 
> Changes for v6:
>               -Added AES and Clk nodes as a sub nodes to the firmware node.
> 
> Changes for v7:
>               -Fixed child nodes format ssues.
> 
> Changes for v8:
>                 -Fixed some minor issues as suggested by rob.
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 89 +++++++++++++++++++
>  1 file changed, 89 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v8 4/5] dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file

[Nava kishore Manne]

The funtionality of xlnx,zynqmp-firmware.txt is replaced with
xlnx,zynqmp-firmware.yaml bindings so this patch removes the
zynqmp-firmware.txt file

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v8:
              -Removed xlnx,zynqmp-firmware.txt as suggested by rob.

 .../firmware/xilinx/xlnx,zynqmp-firmware.txt  | 44 -------------------
 1 file changed, 44 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
deleted file mode 100644
index 18c3aea90df2..000000000000
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
+++ /dev/null
@@ -1,44 +0,0 @@
------------------------------------------------------------------
-Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
------------------------------------------------------------------
-
-The zynqmp-firmware node describes the interface to platform firmware.
-ZynqMP has an interface to communicate with secure firmware. Firmware
-driver provides an interface to firmware APIs. Interface APIs can be
-used by any driver to communicate to PMUFW(Platform Management Unit).
-These requests include clock management, pin control, device control,
-power management service, FPGA service and other platform management
-services.
-
-Required properties:
- - compatible:	Must contain any of below:
-		"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
-		"xlnx,versal-firmware" for Versal
- - method:	The method of calling the PM-API firmware layer.
-		Permitted values are:
-		  - "smc" : SMC #0, following the SMCCC
-		  - "hvc" : HVC #0, following the SMCCC
-
--------
-Example
--------
-
-Zynq Ultrascale+ MPSoC
-----------------------
-firmware {
-	zynqmp_firmware: zynqmp-firmware {
-		compatible = "xlnx,zynqmp-firmware";
-		method = "smc";
-		...
-	};
-};
-
-Versal
-------
-firmware {
-	versal_firmware: versal-firmware {
-		compatible = "xlnx,versal-firmware";
-		method = "smc";
-		...
-	};
-};
-- 
2.17.1

Re: [PATCH v8 4/5] dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file

[Tom Rix]

On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> The funtionality of xlnx,zynqmp-firmware.txt is replaced with

functionality

Tom

> xlnx,zynqmp-firmware.yaml bindings so this patch removes the
> zynqmp-firmware.txt file
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v8:
>                -Removed xlnx,zynqmp-firmware.txt as suggested by rob.
>
>   .../firmware/xilinx/xlnx,zynqmp-firmware.txt  | 44 -------------------
>   1 file changed, 44 deletions(-)
>   delete mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
>
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
> deleted file mode 100644
> index 18c3aea90df2..000000000000
> --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
> +++ /dev/null
> @@ -1,44 +0,0 @@
> ------------------------------------------------------------------
> -Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
> ------------------------------------------------------------------
> -
> -The zynqmp-firmware node describes the interface to platform firmware.
> -ZynqMP has an interface to communicate with secure firmware. Firmware
> -driver provides an interface to firmware APIs. Interface APIs can be
> -used by any driver to communicate to PMUFW(Platform Management Unit).
> -These requests include clock management, pin control, device control,
> -power management service, FPGA service and other platform management
> -services.
> -
> -Required properties:
> - - compatible:	Must contain any of below:
> -		"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
> -		"xlnx,versal-firmware" for Versal
> - - method:	The method of calling the PM-API firmware layer.
> -		Permitted values are:
> -		  - "smc" : SMC #0, following the SMCCC
> -		  - "hvc" : HVC #0, following the SMCCC
> -
> --------
> -Example
> --------
> -
> -Zynq Ultrascale+ MPSoC
> -----------------------
> -firmware {
> -	zynqmp_firmware: zynqmp-firmware {
> -		compatible = "xlnx,zynqmp-firmware";
> -		method = "smc";
> -		...
> -	};
> -};
> -
> -Versal
> -------
> -firmware {
> -	versal_firmware: versal-firmware {
> -		compatible = "xlnx,versal-firmware";
> -		method = "smc";
> -		...
> -	};
> -};

RE: [PATCH v8 4/5] dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file

[Nava kishore Manne]

Hi Tom, 

	Please find my response inline.

> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Wednesday, July 7, 2021 2:39 AM
> To: Nava kishore Manne <navam@xilinx.com>; robh+dt@kernel.org; Michal
> Simek <michals@xilinx.com>; mdf@kernel.org; arnd@arndb.de; Rajan Vaja
> <RAJANV@xilinx.com>; gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <ravipate@xlnx.xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v8 4/5] dt-bindings: firmware: Remove xlnx,zynqmp-
> firmware.txt file
> 
> 
> On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> > The funtionality of xlnx,zynqmp-firmware.txt is replaced with
> 
> functionality
> 

Will fix

Regards,
Navakishore.

Re: [PATCH v8 4/5] dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file

[Rob Herring]

On Sat, 26 Jun 2021 21:22:47 +0530, Nava kishore Manne wrote:
> The funtionality of xlnx,zynqmp-firmware.txt is replaced with
> xlnx,zynqmp-firmware.yaml bindings so this patch removes the
> zynqmp-firmware.txt file
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v8:
>               -Removed xlnx,zynqmp-firmware.txt as suggested by rob.
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.txt  | 44 -------------------
>  1 file changed, 44 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH v8 5/5] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
              -Updated the Fpga Mgr registrations call's
               to 5.11
              -Fixed some minor coding issues as suggested by
               Moritz.

Changes for v3:
              -Rewritten the Versal fpga Kconfig contents.

Changes for v4:
              -Rebased the changes on linux-next.
               No functional changes.

Changes for v5:
              -None.

Changes for v6:
              -None.

Changes for v7:
              -Updated driver to remove unwated priv struct dependency.

Changes for v8:
              -None.

 drivers/fpga/Kconfig       |  9 ++++
 drivers/fpga/Makefile      |  1 +
 drivers/fpga/versal-fpga.c | 96 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 106 insertions(+)
 create mode 100644 drivers/fpga/versal-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 8cd454ee20c0..16793bfc2bb4 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
 	  to configure the programmable logic(PL) through PS
 	  on ZynqMP SoC.
 
+config FPGA_MGR_VERSAL_FPGA
+	tristate "Xilinx Versal FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  Select this option to enable FPGA manager driver support for
+	  Xilinx Versal SoC. This driver uses the firmware interface to
+	  configure the programmable logic(PL).
+
+	  To compile this as a module, choose M here.
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a..0bff783d1b61 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index 000000000000..1bd312a31b23
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	dma_addr_t dma_addr = 0;
+	char *kbuf;
+	int ret;
+
+	kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+	dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+	.state = versal_fpga_ops_state,
+	.write_init = versal_fpga_ops_write_init,
+	.write = versal_fpga_ops_write,
+	.write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fpga_manager *mgr;
+	int ret;
+
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret < 0) {
+		dev_err(dev, "no usable DMA configuration\n");
+		return ret;
+	}
+
+	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+				   &versal_fpga_ops, NULL);
+	if (!mgr)
+		return -ENOMEM;
+
+	return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+	{ .compatible = "xlnx,versal-fpga", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_driver = {
+	.probe = versal_fpga_probe,
+	.driver = {
+		.name = "versal_fpga_manager",
+		.of_match_table = of_match_ptr(versal_fpga_of_match),
+	},
+};
+module_platform_driver(versal_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
+MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.17.1

Re: [PATCH v8 5/5] fpga: versal-fpga: Add versal fpga manager driver

[Tom Rix]

On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> Add support for Xilinx Versal FPGA manager.
>
> PDI source type can be DDR, OCM, QSPI flash etc..
> But driver allocates memory always from DDR, Since driver supports only
> DDR source type.
>
> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> Changes for v2:
>                -Updated the Fpga Mgr registrations call's
>                 to 5.11
>                -Fixed some minor coding issues as suggested by
>                 Moritz.
>
> Changes for v3:
>                -Rewritten the Versal fpga Kconfig contents.
>
> Changes for v4:
>                -Rebased the changes on linux-next.
>                 No functional changes.
>
> Changes for v5:
>                -None.
>
> Changes for v6:
>                -None.
>
> Changes for v7:
>                -Updated driver to remove unwated priv struct dependency.
>
> Changes for v8:
>                -None.
>
>   drivers/fpga/Kconfig       |  9 ++++
>   drivers/fpga/Makefile      |  1 +
>   drivers/fpga/versal-fpga.c | 96 ++++++++++++++++++++++++++++++++++++++
>   3 files changed, 106 insertions(+)
>   create mode 100644 drivers/fpga/versal-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 8cd454ee20c0..16793bfc2bb4 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
>   	  to configure the programmable logic(PL) through PS
>   	  on ZynqMP SoC.
>   
> +config FPGA_MGR_VERSAL_FPGA
> +	tristate "Xilinx Versal FPGA"
> +	depends on ARCH_ZYNQMP || COMPILE_TEST
Shouldn't this depend on ZYNQMP_FIRMWARE ?
> +	help
> +	  Select this option to enable FPGA manager driver support for
> +	  Xilinx Versal SoC. This driver uses the firmware interface to
> +	  configure the programmable logic(PL).
> +
> +	  To compile this as a module, choose M here.
>   endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885883a..0bff783d1b61 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
>   obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
>   obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
>   obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
The other CONFIG_FPGA_MGR* configs are alphabetical, versal should follow.
>   obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>   obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>   
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> new file mode 100644
> index 000000000000..1bd312a31b23
> --- /dev/null
> +++ b/drivers/fpga/versal-fpga.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019-2021 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> +				      struct fpga_image_info *info,
> +				      const char *buf, size_t size)
> +{
> +	return 0;
> +}
> +
These empty ops should go away with my wrappers patchset
> +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> +				 const char *buf, size_t size)
> +{
> +	dma_addr_t dma_addr = 0;
> +	char *kbuf;
> +	int ret;
> +
> +	kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
> +	if (!kbuf)
> +		return -ENOMEM;
> +
> +	memcpy(kbuf, buf, size);
> +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
why isn't the size passed ?
> +	dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
> +
> +	return ret;
> +}
> +
> +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> +					  struct fpga_image_info *info)
> +{
> +	return 0;
> +}
> +
> +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
> +{
> +	return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static const struct fpga_manager_ops versal_fpga_ops = {
> +	.state = versal_fpga_ops_state,
> +	.write_init = versal_fpga_ops_write_init,
> +	.write = versal_fpga_ops_write,
> +	.write_complete = versal_fpga_ops_write_complete,
> +};
> +
> +static int versal_fpga_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct fpga_manager *mgr;
> +	int ret;
> +
> +	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
> +	if (ret < 0) {
> +		dev_err(dev, "no usable DMA configuration\n");
> +		return ret;
> +	}
> +
> +	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
> +				   &versal_fpga_ops, NULL);
> +	if (!mgr)
> +		return -ENOMEM;
> +
> +	return devm_fpga_mgr_register(dev, mgr);
> +}
> +
> +static const struct of_device_id versal_fpga_of_match[] = {
> +	{ .compatible = "xlnx,versal-fpga", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
needs #if defined(CONFIG_OF) wrapper
> +
> +static struct platform_driver versal_fpga_driver = {
> +	.probe = versal_fpga_probe,
> +	.driver = {
> +		.name = "versal_fpga_manager",
> +		.of_match_table = of_match_ptr(versal_fpga_of_match),
> +	},
> +};
> +module_platform_driver(versal_fpga_driver);
> +
> +MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
> +MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");

Rao - needs to be capitalized ?

Tom

> +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
> +MODULE_LICENSE("GPL");

RE: [PATCH v8 5/5] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Hi Tom,

	Please find my response inline.

> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Wednesday, July 7, 2021 3:04 AM
> To: Nava kishore Manne <navam@xilinx.com>; robh+dt@kernel.org; Michal
> Simek <michals@xilinx.com>; mdf@kernel.org; arnd@arndb.de; Rajan Vaja
> <RAJANV@xilinx.com>; gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <ravipate@xlnx.xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Cc: Appana Durga Kedareswara Rao <appanad@xilinx.com>
> Subject: Re: [PATCH v8 5/5] fpga: versal-fpga: Add versal fpga manager driver
> 
> 
> On 6/26/21 8:52 AM, Nava kishore Manne wrote:
> > Add support for Xilinx Versal FPGA manager.
> >
> > PDI source type can be DDR, OCM, QSPI flash etc..
> > But driver allocates memory always from DDR, Since driver supports
> > only DDR source type.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> > <appana.durga.rao@xilinx.com>
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > ---
> > Changes for v2:
> >                -Updated the Fpga Mgr registrations call's
> >                 to 5.11
> >                -Fixed some minor coding issues as suggested by
> >                 Moritz.
> >
> > Changes for v3:
> >                -Rewritten the Versal fpga Kconfig contents.
> >
> > Changes for v4:
> >                -Rebased the changes on linux-next.
> >                 No functional changes.
> >
> > Changes for v5:
> >                -None.
> >
> > Changes for v6:
> >                -None.
> >
> > Changes for v7:
> >                -Updated driver to remove unwated priv struct dependency.
> >
> > Changes for v8:
> >                -None.
> >
> >   drivers/fpga/Kconfig       |  9 ++++
> >   drivers/fpga/Makefile      |  1 +
> >   drivers/fpga/versal-fpga.c | 96
> ++++++++++++++++++++++++++++++++++++++
> >   3 files changed, 106 insertions(+)
> >   create mode 100644 drivers/fpga/versal-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 8cd454ee20c0..16793bfc2bb4 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> >   	  to configure the programmable logic(PL) through PS
> >   	  on ZynqMP SoC.
> >
> > +config FPGA_MGR_VERSAL_FPGA
> > +	tristate "Xilinx Versal FPGA"
> > +	depends on ARCH_ZYNQMP || COMPILE_TEST
> Shouldn't this depend on ZYNQMP_FIRMWARE ?

Yes it has a dependency, will fix

> > +	help
> > +	  Select this option to enable FPGA manager driver support for
> > +	  Xilinx Versal SoC. This driver uses the firmware interface to
> > +	  configure the programmable logic(PL).
> > +
> > +	  To compile this as a module, choose M here.
> >   endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 18dc9885883a..0bff783d1b61 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+=
> ts73xx-fpga.o
> >   obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> >   obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
> >   obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
> The other CONFIG_FPGA_MGR* configs are alphabetical, versal should
> follow.

Will fix.

> >   obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >   obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > new file mode 100644 index 000000000000..1bd312a31b23
> > --- /dev/null
> > +++ b/drivers/fpga/versal-fpga.c
> > @@ -0,0 +1,96 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019-2021 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > +				      struct fpga_image_info *info,
> > +				      const char *buf, size_t size) {
> > +	return 0;
> > +}
> > +
> These empty ops should go away with my wrappers patchset

Once your patches got integrated will post one more patch to remove this empty ops.

> > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > +				 const char *buf, size_t size)
> > +{
> > +	dma_addr_t dma_addr = 0;
> > +	char *kbuf;
> > +	int ret;
> > +
> > +	kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr,
> GFP_KERNEL);
> > +	if (!kbuf)
> > +		return -ENOMEM;
> > +
> > +	memcpy(kbuf, buf, size);
> > +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> why isn't the size passed ?


Size is part of PDI images header users no need to pass this info explicitly.

> > +	dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
> > +
> > +	return ret;
> > +}
> > +
> > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> > +					  struct fpga_image_info *info)
> > +{
> > +	return 0;
> > +}
> > +
> > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager
> > +*mgr) {
> > +	return FPGA_MGR_STATE_UNKNOWN;
> > +}
> > +
> > +static const struct fpga_manager_ops versal_fpga_ops = {
> > +	.state = versal_fpga_ops_state,
> > +	.write_init = versal_fpga_ops_write_init,
> > +	.write = versal_fpga_ops_write,
> > +	.write_complete = versal_fpga_ops_write_complete, };
> > +
> > +static int versal_fpga_probe(struct platform_device *pdev) {
> > +	struct device *dev = &pdev->dev;
> > +	struct fpga_manager *mgr;
> > +	int ret;
> > +
> > +	ret = dma_set_mask_and_coherent(&pdev->dev,
> DMA_BIT_MASK(32));
> > +	if (ret < 0) {
> > +		dev_err(dev, "no usable DMA configuration\n");
> > +		return ret;
> > +	}
> > +
> > +	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
> > +				   &versal_fpga_ops, NULL);
> > +	if (!mgr)
> > +		return -ENOMEM;
> > +
> > +	return devm_fpga_mgr_register(dev, mgr); }
> > +
> > +static const struct of_device_id versal_fpga_of_match[] = {
> > +	{ .compatible = "xlnx,versal-fpga", },
> > +	{},
> > +};
> > +MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
> needs #if defined(CONFIG_OF) wrapper

Will fix.

> > +
> > +static struct platform_driver versal_fpga_driver = {
> > +	.probe = versal_fpga_probe,
> > +	.driver = {
> > +		.name = "versal_fpga_manager",
> > +		.of_match_table = of_match_ptr(versal_fpga_of_match),
> > +	},
> > +};
> > +module_platform_driver(versal_fpga_driver);
> > +
> > +MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
> > +MODULE_AUTHOR("Appana Durga Kedareswara rao
> > +<appanad.durga.rao@xilinx.com>");
> 
> Rao - needs to be capitalized ?
> 

Will fix.