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* [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC
@ 2021-06-25  7:42 Martin Hundebøll
  2021-06-25  7:42 ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Martin Hundebøll
                   ` (4 more replies)
  0 siblings, 5 replies; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

This is an initial set of patches for the Silciom N5010 programmable
accelerated card adding support for reading out sensors.

Based on v5.13-rc7

Changes since v1:
 * Commit message in patch 1 is updated with card description
 * Added Hao's Acked-by to patch 1
 * Patch 2 is replaced with a new patch to carry feature revision info
   in struct dfl_device
 * Patch 3 is updated to use feature revision from struct dfl_device
 * Patch 4 from v0 is split into separate patches for hwmon and mfd

Martin Hundebøll (5):
  fpga: dfl: pci: add device IDs for Silicom N501x PAC cards
  fpga: dfl: expose feature revision from struct dfl_device
  spi: spi-altera-dfl: support n5010 feature revision
  mfd: intel-m10-bmc: add n5010 variant
  hwmon: intel-m10-bmc-hwmon: add n5010 sensors

 drivers/fpga/dfl-pci.c              |   5 ++
 drivers/fpga/dfl.c                  |  27 ++++---
 drivers/fpga/dfl.h                  |   1 +
 drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
 drivers/mfd/intel-m10-bmc.c         |  12 ++-
 drivers/spi/spi-altera-dfl.c        |  15 +++-
 include/linux/dfl.h                 |   1 +
 7 files changed, 164 insertions(+), 13 deletions(-)

-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards
  2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
@ 2021-06-25  7:42 ` Martin Hundebøll
  2021-06-25 18:43   ` Moritz Fischer
  2021-06-25  7:42 ` [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

This adds the approved PCI Express Device IDs for the Silicom PAC N5010
and N5011 cards (aka. Silicom Lightning Creek cards).

The N5010 features an FPGA that manages/interfaces four QSFP ports, and
allows on-board custom packet processing/filtering/routing, based on
logic loaded with user-provided FPGA bitstreams.

The N5011 cards adds a PCIe switch that exposes, in addition to the FPGA
itself, two Intel E810 (aka Columbiaville) ethernet controllers. With
this, packets can be forwarded from the FPGA to the host for further
processing.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
Acked-by: Wu Hao <hao.wu@intel.com>
---

Changes since v1:
 * Commit message is updated with card description
 * Added Hao's Acked-by

 drivers/fpga/dfl-pci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index b44523ea8c91..4d68719e608f 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -74,6 +74,9 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
 #define PCIE_DEVICE_ID_PF_DSC_1_X		0x09C4
 #define PCIE_DEVICE_ID_INTEL_PAC_N3000		0x0B30
 #define PCIE_DEVICE_ID_INTEL_PAC_D5005		0x0B2B
+#define PCIE_DEVICE_ID_SILICOM_PAC_N5010	0x1000
+#define PCIE_DEVICE_ID_SILICOM_PAC_N5011	0x1001
+
 /* VF Device */
 #define PCIE_DEVICE_ID_VF_INT_5_X		0xBCBF
 #define PCIE_DEVICE_ID_VF_INT_6_X		0xBCC1
@@ -90,6 +93,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
+	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
+	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
 	{0,}
 };
 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device
  2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
  2021-06-25  7:42 ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Martin Hundebøll
@ 2021-06-25  7:42 ` Martin Hundebøll
  2021-06-25 19:26   ` Moritz Fischer
  2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

Drivers can make use of the feature field from the DFL header, but
shouldn't know about the header structure. To avoid exposing such info,
and to reduce the number of reads from the io-mem, the revision is added
to struct dfl_device.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
---

Changes since v1:
 * This patch replaces the previous patch 2 and exposes the feature
   revision through struct dfl_device instead of a helper reading from
   io-mem

 drivers/fpga/dfl.c  | 27 +++++++++++++++++----------
 drivers/fpga/dfl.h  |  1 +
 include/linux/dfl.h |  1 +
 3 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 511b20ff35a3..9381c579d1cd 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata,
 
 	ddev->type = feature_dev_id_type(pdev);
 	ddev->feature_id = feature->id;
+	ddev->revision = feature->revision;
 	ddev->cdev = pdata->dfl_cdev;
 
 	/* add mmio resource */
@@ -717,6 +718,7 @@ struct build_feature_devs_info {
  */
 struct dfl_feature_info {
 	u16 fid;
+	u8 rev;
 	struct resource mmio_res;
 	void __iomem *ioaddr;
 	struct list_head node;
@@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 		/* save resource information for each feature */
 		feature->dev = fdev;
 		feature->id = finfo->fid;
+		feature->revision = finfo->rev;
 
 		/*
 		 * the FIU header feature has some fundamental functions (sriov
@@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo)
 	devm_kfree(binfo->dev, binfo);
 }
 
-static inline u32 feature_size(void __iomem *start)
+static inline u32 feature_size(u64 value)
 {
-	u64 v = readq(start + DFH);
-	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
+	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value);
 	/* workaround for private features with invalid size, use 4K instead */
 	return ofst ? ofst : 4096;
 }
 
-static u16 feature_id(void __iomem *start)
+static u16 feature_id(u64 value)
 {
-	u64 v = readq(start + DFH);
-	u16 id = FIELD_GET(DFH_ID, v);
-	u8 type = FIELD_GET(DFH_TYPE, v);
+	u16 id = FIELD_GET(DFH_ID, value);
+	u8 type = FIELD_GET(DFH_TYPE, value);
 
 	if (type == DFH_TYPE_FIU)
 		return FEATURE_ID_FIU_HEADER;
@@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo,
 	unsigned int irq_base, nr_irqs;
 	struct dfl_feature_info *finfo;
 	int ret;
+	u8 rev;
+	u64 v;
+
+	v = readq(binfo->ioaddr + ofst);
+	rev = FIELD_GET(DFH_REVISION, v);
 
 	/* read feature size and id if inputs are invalid */
-	size = size ? size : feature_size(binfo->ioaddr + ofst);
-	fid = fid ? fid : feature_id(binfo->ioaddr + ofst);
+	size = size ? size : feature_size(v);
+	fid = fid ? fid : feature_id(v);
 
 	if (binfo->len - ofst < size)
 		return -EINVAL;
@@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo,
 		return -ENOMEM;
 
 	finfo->fid = fid;
+	finfo->rev = rev;
 	finfo->mmio_res.start = binfo->start + ofst;
 	finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
 	finfo->mmio_res.flags = IORESOURCE_MEM;
@@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo,
 {
 	if (!is_feature_dev_detected(binfo)) {
 		dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n",
-			feature_id(binfo->ioaddr + ofst));
+			feature_id(readq(binfo->ioaddr + ofst)));
 		return -EINVAL;
 	}
 
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 2b82c96ba56c..422157cfd742 100644
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx {
 struct dfl_feature {
 	struct platform_device *dev;
 	u16 id;
+	u8 revision;
 	int resource_index;
 	void __iomem *ioaddr;
 	struct dfl_feature_irq_ctx *irq_ctx;
diff --git a/include/linux/dfl.h b/include/linux/dfl.h
index 6cc10982351a..431636a0dc78 100644
--- a/include/linux/dfl.h
+++ b/include/linux/dfl.h
@@ -38,6 +38,7 @@ struct dfl_device {
 	int id;
 	u16 type;
 	u16 feature_id;
+	u8 revision;
 	struct resource mmio_res;
 	int *irqs;
 	unsigned int num_irqs;
-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
  2021-06-25  7:42 ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Martin Hundebøll
  2021-06-25  7:42 ` [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
@ 2021-06-25  7:42 ` Martin Hundebøll
  2021-06-28  5:58   ` Xu Yilun
  2021-06-28 17:39   ` Moritz Fischer
  2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
  2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
  4 siblings, 2 replies; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

The Max10 BMC on the Silicom n5010 PAC is slightly different than the
existing BMC's, so use a dedicated feature revision detect it.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
---

Changes since v1:
 * use feature revision from struct dfl_device instead of reading it
   from io-mem

 drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
index 3e32e4fe5895..f6cf7c8d9dac 100644
--- a/drivers/spi/spi-altera-dfl.c
+++ b/drivers/spi/spi-altera-dfl.c
@@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
 	.chip_select = 0,
 };
 
+static struct spi_board_info m10_n5010_bmc_info = {
+	.modalias = "m10-n5010",
+	.max_speed_hz = 12500000,
+	.bus_num = 0,
+	.chip_select = 0,
+};
+
 static void config_spi_master(void __iomem *base, struct spi_master *master)
 {
 	u64 v;
@@ -130,6 +137,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master)
 
 static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
 {
+	struct spi_board_info *board_info = &m10_bmc_info;
 	struct device *dev = &dfl_dev->dev;
 	struct spi_master *master;
 	struct altera_spi *hw;
@@ -172,9 +180,12 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
 		goto exit;
 	}
 
-	if (!spi_new_device(master,  &m10_bmc_info)) {
+	if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010)
+		board_info = &m10_n5010_bmc_info;
+
+	if (!spi_new_device(master, board_info)) {
 		dev_err(dev, "%s failed to create SPI device: %s\n",
-			__func__, m10_bmc_info.modalias);
+			__func__, board_info->modalias);
 	}
 
 	return 0;
-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
                   ` (2 preceding siblings ...)
  2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
@ 2021-06-25  7:42 ` Martin Hundebøll
  2021-06-25 18:45   ` Moritz Fischer
                     ` (2 more replies)
  2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
  4 siblings, 3 replies; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

 The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
 m10bmc types.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
---

Changes since v1:
 * Patch split out to separate mfd changes

 drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
index 1a9bfb7f48cd..8db3bcf5fccc 100644
--- a/drivers/mfd/intel-m10-bmc.c
+++ b/drivers/mfd/intel-m10-bmc.c
@@ -15,7 +15,8 @@
 
 enum m10bmc_type {
 	M10_N3000,
-	M10_D5005
+	M10_D5005,
+	M10_N5010,
 };
 
 static struct mfd_cell m10bmc_d5005_subdevs[] = {
@@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
 	{ .name = "n3000bmc-secure" },
 };
 
+static struct mfd_cell m10bmc_n5010_subdevs[] = {
+	{ .name = "n5010bmc-hwmon" },
+};
+
 static const struct regmap_range m10bmc_regmap_range[] = {
 	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
 	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
@@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
 		cells = m10bmc_d5005_subdevs;
 		n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
 		break;
+	case M10_N5010:
+		cells = m10bmc_n5010_subdevs;
+		n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
+		break;
 	default:
 		return -ENODEV;
 	}
@@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
 static const struct spi_device_id m10bmc_spi_id[] = {
 	{ "m10-n3000", M10_N3000 },
 	{ "m10-d5005", M10_D5005 },
+	{ "m10-n5010", M10_N5010 },
 	{ }
 };
 MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
                   ` (3 preceding siblings ...)
  2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
@ 2021-06-25  7:42 ` Martin Hundebøll
  2021-06-28  6:00   ` Xu Yilun
  2021-06-28 16:35   ` Guenter Roeck
  4 siblings, 2 replies; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-25  7:42 UTC (permalink / raw)
  To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown
  Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi

From: Martin Hundebøll <mhu@silicom.dk>

Add the list of sensors supported by the Silicom n5010 PAC, and enable
the drivers as a subtype of the intel-m10-bmc multi-function driver.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
---

Changes since v1:
 * Patch split out to separate hwmon changes

 drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
index bd7ed2ed3a1e..7a08e4c44a4b 100644
--- a/drivers/hwmon/intel-m10-bmc-hwmon.c
+++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
@@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
 	.hinfo = d5005bmc_hinfo,
 };
 
+static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
+	{ 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
+	{ 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
+	{ 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
+	{ 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
+	{ 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
+	{ 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
+	{ 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
+	{ 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
+	{ 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
+	{ 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
+	{ 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
+	{ 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
+	{ 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
+	{ 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
+	{ 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
+	{ 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
+	{ 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
+};
+
+static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
+	{ 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
+	{ 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
+	{ 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
+	{ 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
+	{ 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
+	{ 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
+	{ 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
+	{ 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
+	{ 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
+	{ 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
+	{ 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
+	{ 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
+	{ 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
+};
+
+static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
+	{ 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
+	{ 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
+	{ 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
+	{ 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
+	{ 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
+	{ 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
+	{ 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
+	{ 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
+	{ 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
+	{ 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
+	{ 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
+	{ 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
+	{ 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
+};
+
+static const struct hwmon_channel_info *n5010bmc_hinfo[] = {
+	HWMON_CHANNEL_INFO(temp,
+			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_INPUT | HWMON_T_LABEL),
+	HWMON_CHANNEL_INFO(in,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LABEL),
+	HWMON_CHANNEL_INFO(curr,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL,
+			   HWMON_C_INPUT | HWMON_C_LABEL),
+	NULL
+};
+
+static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
+	.tables = {
+		[hwmon_temp] = n5010bmc_temp_tbl,
+		[hwmon_in] = n5010bmc_in_tbl,
+		[hwmon_curr] = n5010bmc_curr_tbl,
+	},
+
+	.hinfo = n5010bmc_hinfo,
+};
+
 static umode_t
 m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
 			u32 attr, int channel)
@@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
 		.name = "d5005bmc-hwmon",
 		.driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
 	},
+	{
+		.name = "n5010bmc-hwmon",
+		.driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
+	},
 	{ }
 };
 
-- 
2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards
  2021-06-25  7:42 ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Martin Hundebøll
@ 2021-06-25 18:43   ` Moritz Fischer
  0 siblings, 0 replies; 25+ messages in thread
From: Moritz Fischer @ 2021-06-25 18:43 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 09:42:09AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> This adds the approved PCI Express Device IDs for the Silicom PAC N5010
> and N5011 cards (aka. Silicom Lightning Creek cards).
> 
> The N5010 features an FPGA that manages/interfaces four QSFP ports, and
> allows on-board custom packet processing/filtering/routing, based on
> logic loaded with user-provided FPGA bitstreams.
> 
> The N5011 cards adds a PCIe switch that exposes, in addition to the FPGA
> itself, two Intel E810 (aka Columbiaville) ethernet controllers. With
> this, packets can be forwarded from the FPGA to the host for further
> processing.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> Acked-by: Wu Hao <hao.wu@intel.com>
> ---
> 
> Changes since v1:
>  * Commit message is updated with card description
>  * Added Hao's Acked-by
> 
>  drivers/fpga/dfl-pci.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> index b44523ea8c91..4d68719e608f 100644
> --- a/drivers/fpga/dfl-pci.c
> +++ b/drivers/fpga/dfl-pci.c
> @@ -74,6 +74,9 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
>  #define PCIE_DEVICE_ID_PF_DSC_1_X		0x09C4
>  #define PCIE_DEVICE_ID_INTEL_PAC_N3000		0x0B30
>  #define PCIE_DEVICE_ID_INTEL_PAC_D5005		0x0B2B
> +#define PCIE_DEVICE_ID_SILICOM_PAC_N5010	0x1000
> +#define PCIE_DEVICE_ID_SILICOM_PAC_N5011	0x1001
> +
>  /* VF Device */
>  #define PCIE_DEVICE_ID_VF_INT_5_X		0xBCBF
>  #define PCIE_DEVICE_ID_VF_INT_6_X		0xBCC1
> @@ -90,6 +93,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
>  	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
>  	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
>  	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
> +	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
>  	{0,}
>  };
>  MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
> -- 
> 2.31.0
> 
Applied to for-next.

Thanks

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
@ 2021-06-25 18:45   ` Moritz Fischer
  2021-06-29  1:39     ` Xu Yilun
  2021-06-28  5:59   ` Xu Yilun
  2021-06-30 10:57   ` Lee Jones
  2 siblings, 1 reply; 25+ messages in thread
From: Moritz Fischer @ 2021-06-25 18:45 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 09:42:12AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
>  The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
>  m10bmc types.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> 
> Changes since v1:
>  * Patch split out to separate mfd changes
> 
>  drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> index 1a9bfb7f48cd..8db3bcf5fccc 100644
> --- a/drivers/mfd/intel-m10-bmc.c
> +++ b/drivers/mfd/intel-m10-bmc.c
> @@ -15,7 +15,8 @@
>  
>  enum m10bmc_type {
>  	M10_N3000,
> -	M10_D5005
> +	M10_D5005,
> +	M10_N5010,
>  };
>  
>  static struct mfd_cell m10bmc_d5005_subdevs[] = {
> @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
>  	{ .name = "n3000bmc-secure" },
>  };
>  
> +static struct mfd_cell m10bmc_n5010_subdevs[] = {
> +	{ .name = "n5010bmc-hwmon" },
> +};
> +
>  static const struct regmap_range m10bmc_regmap_range[] = {
>  	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
>  	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
> @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>  		cells = m10bmc_d5005_subdevs;
>  		n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
>  		break;
> +	case M10_N5010:
> +		cells = m10bmc_n5010_subdevs;
> +		n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
> +		break;
>  	default:
>  		return -ENODEV;
>  	}
> @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>  static const struct spi_device_id m10bmc_spi_id[] = {
>  	{ "m10-n3000", M10_N3000 },
>  	{ "m10-d5005", M10_D5005 },
> +	{ "m10-n5010", M10_N5010 },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
> -- 
> 2.31.0
> 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device
  2021-06-25  7:42 ` [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
@ 2021-06-25 19:26   ` Moritz Fischer
  2021-06-28  3:38     ` Wu, Hao
  0 siblings, 1 reply; 25+ messages in thread
From: Moritz Fischer @ 2021-06-25 19:26 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 09:42:10AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> Drivers can make use of the feature field from the DFL header, but
> shouldn't know about the header structure. To avoid exposing such info,
> and to reduce the number of reads from the io-mem, the revision is added
> to struct dfl_device.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * This patch replaces the previous patch 2 and exposes the feature
>    revision through struct dfl_device instead of a helper reading from
>    io-mem
> 
>  drivers/fpga/dfl.c  | 27 +++++++++++++++++----------
>  drivers/fpga/dfl.h  |  1 +
>  include/linux/dfl.h |  1 +
>  3 files changed, 19 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index 511b20ff35a3..9381c579d1cd 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata,
>  
>  	ddev->type = feature_dev_id_type(pdev);
>  	ddev->feature_id = feature->id;
> +	ddev->revision = feature->revision;
>  	ddev->cdev = pdata->dfl_cdev;
>  
>  	/* add mmio resource */
> @@ -717,6 +718,7 @@ struct build_feature_devs_info {
>   */
>  struct dfl_feature_info {
>  	u16 fid;
> +	u8 rev;
>  	struct resource mmio_res;
>  	void __iomem *ioaddr;
>  	struct list_head node;
> @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
>  		/* save resource information for each feature */
>  		feature->dev = fdev;
>  		feature->id = finfo->fid;
> +		feature->revision = finfo->rev;
>  
>  		/*
>  		 * the FIU header feature has some fundamental functions (sriov
> @@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo)
>  	devm_kfree(binfo->dev, binfo);
>  }
>  
> -static inline u32 feature_size(void __iomem *start)
> +static inline u32 feature_size(u64 value)
>  {
> -	u64 v = readq(start + DFH);
> -	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
> +	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value);
>  	/* workaround for private features with invalid size, use 4K instead */
>  	return ofst ? ofst : 4096;
>  }
>  
> -static u16 feature_id(void __iomem *start)
> +static u16 feature_id(u64 value)
>  {
> -	u64 v = readq(start + DFH);
> -	u16 id = FIELD_GET(DFH_ID, v);
> -	u8 type = FIELD_GET(DFH_TYPE, v);
> +	u16 id = FIELD_GET(DFH_ID, value);
> +	u8 type = FIELD_GET(DFH_TYPE, value);
>  
>  	if (type == DFH_TYPE_FIU)
>  		return FEATURE_ID_FIU_HEADER;
> @@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo,
>  	unsigned int irq_base, nr_irqs;
>  	struct dfl_feature_info *finfo;
>  	int ret;
> +	u8 rev;
> +	u64 v;
> +
> +	v = readq(binfo->ioaddr + ofst);
> +	rev = FIELD_GET(DFH_REVISION, v);
>  
>  	/* read feature size and id if inputs are invalid */
> -	size = size ? size : feature_size(binfo->ioaddr + ofst);
> -	fid = fid ? fid : feature_id(binfo->ioaddr + ofst);
> +	size = size ? size : feature_size(v);
> +	fid = fid ? fid : feature_id(v);
>  
>  	if (binfo->len - ofst < size)
>  		return -EINVAL;
> @@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo,
>  		return -ENOMEM;
>  
>  	finfo->fid = fid;
> +	finfo->rev = rev;
>  	finfo->mmio_res.start = binfo->start + ofst;
>  	finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
>  	finfo->mmio_res.flags = IORESOURCE_MEM;
> @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo,
>  {
>  	if (!is_feature_dev_detected(binfo)) {
>  		dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n",
> -			feature_id(binfo->ioaddr + ofst));
> +			feature_id(readq(binfo->ioaddr + ofst)));
>  		return -EINVAL;
>  	}
>  
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 2b82c96ba56c..422157cfd742 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx {
>  struct dfl_feature {
>  	struct platform_device *dev;
>  	u16 id;
> +	u8 revision;
>  	int resource_index;
>  	void __iomem *ioaddr;
>  	struct dfl_feature_irq_ctx *irq_ctx;
> diff --git a/include/linux/dfl.h b/include/linux/dfl.h
> index 6cc10982351a..431636a0dc78 100644
> --- a/include/linux/dfl.h
> +++ b/include/linux/dfl.h
> @@ -38,6 +38,7 @@ struct dfl_device {
>  	int id;
>  	u16 type;
>  	u16 feature_id;
> +	u8 revision;
>  	struct resource mmio_res;
>  	int *irqs;
>  	unsigned int num_irqs;
> -- 
> 2.31.0
> 
Looks good to me, any concerns from Intel folks?

- Moritz

^ permalink raw reply	[flat|nested] 25+ messages in thread

* RE: [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device
  2021-06-25 19:26   ` Moritz Fischer
@ 2021-06-28  3:38     ` Wu, Hao
  0 siblings, 0 replies; 25+ messages in thread
From: Wu, Hao @ 2021-06-28  3:38 UTC (permalink / raw)
  To: Moritz Fischer, Martin Hundebøll, Xu, Yilun
  Cc: Tom Rix, Jean Delvare, Guenter Roeck, Lee Jones, Mark Brown,
	Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon,
	linux-spi

> On Fri, Jun 25, 2021 at 09:42:10AM +0200, Martin Hundebøll wrote:
> > From: Martin Hundebøll <mhu@silicom.dk>
> >
> > Drivers can make use of the feature field from the DFL header, but
> > shouldn't know about the header structure. To avoid exposing such info,
> > and to reduce the number of reads from the io-mem, the revision is added
> > to struct dfl_device.

DFL driver may need to access DFL header (if device specific fields added in
the future) but at least no need for common fields. It sounds a little confusing
to people, that the purpose of this patch is not to avoid exposing such info.

How about this one:

DFL device drivers have common need of checking revision information from
DFL header, as well as other DFL common information like feature id and type.
So this patch exposes revision information directly via DFL device data structure.
As DFL core code has already read DFL header, so this patch saves additional DFL
header mmio reads from DFL device drivers too.

Other places look good to me.

Thanks
Hao

> >
> > Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> > ---
> >
> > Changes since v1:
> >  * This patch replaces the previous patch 2 and exposes the feature
> >    revision through struct dfl_device instead of a helper reading from
> >    io-mem
> >
> >  drivers/fpga/dfl.c  | 27 +++++++++++++++++----------
> >  drivers/fpga/dfl.h  |  1 +
> >  include/linux/dfl.h |  1 +
> >  3 files changed, 19 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> > index 511b20ff35a3..9381c579d1cd 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata,
> >
> >  	ddev->type = feature_dev_id_type(pdev);
> >  	ddev->feature_id = feature->id;
> > +	ddev->revision = feature->revision;
> >  	ddev->cdev = pdata->dfl_cdev;
> >
> >  	/* add mmio resource */
> > @@ -717,6 +718,7 @@ struct build_feature_devs_info {
> >   */
> >  struct dfl_feature_info {
> >  	u16 fid;
> > +	u8 rev;
> >  	struct resource mmio_res;
> >  	void __iomem *ioaddr;
> >  	struct list_head node;
> > @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct
> build_feature_devs_info *binfo)
> >  		/* save resource information for each feature */
> >  		feature->dev = fdev;
> >  		feature->id = finfo->fid;
> > +		feature->revision = finfo->rev;
> >
> >  		/*
> >  		 * the FIU header feature has some fundamental functions
> (sriov
> > @@ -910,19 +913,17 @@ static void build_info_free(struct
> build_feature_devs_info *binfo)
> >  	devm_kfree(binfo->dev, binfo);
> >  }
> >
> > -static inline u32 feature_size(void __iomem *start)
> > +static inline u32 feature_size(u64 value)
> >  {
> > -	u64 v = readq(start + DFH);
> > -	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
> > +	u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value);
> >  	/* workaround for private features with invalid size, use 4K instead */
> >  	return ofst ? ofst : 4096;
> >  }
> >
> > -static u16 feature_id(void __iomem *start)
> > +static u16 feature_id(u64 value)
> >  {
> > -	u64 v = readq(start + DFH);
> > -	u16 id = FIELD_GET(DFH_ID, v);
> > -	u8 type = FIELD_GET(DFH_TYPE, v);
> > +	u16 id = FIELD_GET(DFH_ID, value);
> > +	u8 type = FIELD_GET(DFH_TYPE, value);
> >
> >  	if (type == DFH_TYPE_FIU)
> >  		return FEATURE_ID_FIU_HEADER;
> > @@ -1021,10 +1022,15 @@ create_feature_instance(struct
> build_feature_devs_info *binfo,
> >  	unsigned int irq_base, nr_irqs;
> >  	struct dfl_feature_info *finfo;
> >  	int ret;
> > +	u8 rev;
> > +	u64 v;
> > +
> > +	v = readq(binfo->ioaddr + ofst);
> > +	rev = FIELD_GET(DFH_REVISION, v);
> >
> >  	/* read feature size and id if inputs are invalid */
> > -	size = size ? size : feature_size(binfo->ioaddr + ofst);
> > -	fid = fid ? fid : feature_id(binfo->ioaddr + ofst);
> > +	size = size ? size : feature_size(v);
> > +	fid = fid ? fid : feature_id(v);
> >
> >  	if (binfo->len - ofst < size)
> >  		return -EINVAL;
> > @@ -1038,6 +1044,7 @@ create_feature_instance(struct
> build_feature_devs_info *binfo,
> >  		return -ENOMEM;
> >
> >  	finfo->fid = fid;
> > +	finfo->rev = rev;
> >  	finfo->mmio_res.start = binfo->start + ofst;
> >  	finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
> >  	finfo->mmio_res.flags = IORESOURCE_MEM;
> > @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct
> build_feature_devs_info *binfo,
> >  {
> >  	if (!is_feature_dev_detected(binfo)) {
> >  		dev_err(binfo->dev, "the private feature 0x%x does not belong
> to any AFU.\n",
> > -			feature_id(binfo->ioaddr + ofst));
> > +			feature_id(readq(binfo->ioaddr + ofst)));
> >  		return -EINVAL;
> >  	}
> >
> > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> > index 2b82c96ba56c..422157cfd742 100644
> > --- a/drivers/fpga/dfl.h
> > +++ b/drivers/fpga/dfl.h
> > @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx {
> >  struct dfl_feature {
> >  	struct platform_device *dev;
> >  	u16 id;
> > +	u8 revision;
> >  	int resource_index;
> >  	void __iomem *ioaddr;
> >  	struct dfl_feature_irq_ctx *irq_ctx;
> > diff --git a/include/linux/dfl.h b/include/linux/dfl.h
> > index 6cc10982351a..431636a0dc78 100644
> > --- a/include/linux/dfl.h
> > +++ b/include/linux/dfl.h
> > @@ -38,6 +38,7 @@ struct dfl_device {
> >  	int id;
> >  	u16 type;
> >  	u16 feature_id;
> > +	u8 revision;
> >  	struct resource mmio_res;
> >  	int *irqs;
> >  	unsigned int num_irqs;
> > --
> > 2.31.0
> >
> Looks good to me, any concerns from Intel folks?
> 
> - Moritz

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
@ 2021-06-28  5:58   ` Xu Yilun
  2021-06-28 17:39   ` Moritz Fischer
  1 sibling, 0 replies; 25+ messages in thread
From: Xu Yilun @ 2021-06-28  5:58 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Jean Delvare, Guenter Roeck,
	Lee Jones, Mark Brown, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

It is good to me.

On Fri, Jun 25, 2021 at 09:42:11AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> The Max10 BMC on the Silicom n5010 PAC is slightly different than the
> existing BMC's, so use a dedicated feature revision detect it.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * use feature revision from struct dfl_device instead of reading it
>    from io-mem
> 
>  drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
> index 3e32e4fe5895..f6cf7c8d9dac 100644
> --- a/drivers/spi/spi-altera-dfl.c
> +++ b/drivers/spi/spi-altera-dfl.c
> @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
>  	.chip_select = 0,
>  };
>  
> +static struct spi_board_info m10_n5010_bmc_info = {
> +	.modalias = "m10-n5010",
> +	.max_speed_hz = 12500000,
> +	.bus_num = 0,
> +	.chip_select = 0,
> +};
> +
>  static void config_spi_master(void __iomem *base, struct spi_master *master)
>  {
>  	u64 v;
> @@ -130,6 +137,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master)
>  
>  static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
>  {
> +	struct spi_board_info *board_info = &m10_bmc_info;
>  	struct device *dev = &dfl_dev->dev;
>  	struct spi_master *master;
>  	struct altera_spi *hw;
> @@ -172,9 +180,12 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
>  		goto exit;
>  	}
>  
> -	if (!spi_new_device(master,  &m10_bmc_info)) {
> +	if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010)
> +		board_info = &m10_n5010_bmc_info;
> +
> +	if (!spi_new_device(master, board_info)) {
>  		dev_err(dev, "%s failed to create SPI device: %s\n",
> -			__func__, m10_bmc_info.modalias);
> +			__func__, board_info->modalias);
>  	}
>  
>  	return 0;
> -- 
> 2.31.0

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
  2021-06-25 18:45   ` Moritz Fischer
@ 2021-06-28  5:59   ` Xu Yilun
  2021-06-28 10:33     ` Lee Jones
  2021-06-30 10:57   ` Lee Jones
  2 siblings, 1 reply; 25+ messages in thread
From: Xu Yilun @ 2021-06-28  5:59 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Jean Delvare, Guenter Roeck,
	Lee Jones, Mark Brown, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

It is good to me.

On Fri, Jun 25, 2021 at 09:42:12AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
>  The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
>  m10bmc types.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * Patch split out to separate mfd changes
> 
>  drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> index 1a9bfb7f48cd..8db3bcf5fccc 100644
> --- a/drivers/mfd/intel-m10-bmc.c
> +++ b/drivers/mfd/intel-m10-bmc.c
> @@ -15,7 +15,8 @@
>  
>  enum m10bmc_type {
>  	M10_N3000,
> -	M10_D5005
> +	M10_D5005,
> +	M10_N5010,
>  };
>  
>  static struct mfd_cell m10bmc_d5005_subdevs[] = {
> @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
>  	{ .name = "n3000bmc-secure" },
>  };
>  
> +static struct mfd_cell m10bmc_n5010_subdevs[] = {
> +	{ .name = "n5010bmc-hwmon" },
> +};
> +
>  static const struct regmap_range m10bmc_regmap_range[] = {
>  	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
>  	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
> @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>  		cells = m10bmc_d5005_subdevs;
>  		n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
>  		break;
> +	case M10_N5010:
> +		cells = m10bmc_n5010_subdevs;
> +		n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
> +		break;
>  	default:
>  		return -ENODEV;
>  	}
> @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
>  static const struct spi_device_id m10bmc_spi_id[] = {
>  	{ "m10-n3000", M10_N3000 },
>  	{ "m10-d5005", M10_D5005 },
> +	{ "m10-n5010", M10_N5010 },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
> -- 
> 2.31.0

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
@ 2021-06-28  6:00   ` Xu Yilun
  2021-06-28 14:11     ` Guenter Roeck
  2021-06-28 16:35   ` Guenter Roeck
  1 sibling, 1 reply; 25+ messages in thread
From: Xu Yilun @ 2021-06-28  6:00 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Jean Delvare, Guenter Roeck,
	Lee Jones, Mark Brown, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

It is good to me.

On Fri, Jun 25, 2021 at 09:42:13AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> Add the list of sensors supported by the Silicom n5010 PAC, and enable
> the drivers as a subtype of the intel-m10-bmc multi-function driver.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * Patch split out to separate hwmon changes
> 
>  drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
> index bd7ed2ed3a1e..7a08e4c44a4b 100644
> --- a/drivers/hwmon/intel-m10-bmc-hwmon.c
> +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
> @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
>  	.hinfo = d5005bmc_hinfo,
>  };
>  
> +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
> +	{ 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
> +	{ 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
> +	{ 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
> +	{ 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
> +	{ 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
> +	{ 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
> +	{ 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
> +	{ 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
> +	{ 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
> +	{ 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
> +	{ 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
> +	{ 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
> +	{ 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
> +	{ 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
> +	{ 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
> +	{ 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
> +	{ 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
> +};
> +
> +static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
> +	{ 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
> +	{ 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
> +	{ 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
> +	{ 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
> +	{ 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
> +	{ 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
> +	{ 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
> +	{ 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
> +	{ 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
> +	{ 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
> +	{ 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
> +	{ 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
> +	{ 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
> +};
> +
> +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
> +	{ 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
> +	{ 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
> +	{ 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
> +	{ 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
> +	{ 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
> +	{ 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
> +	{ 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
> +	{ 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
> +	{ 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
> +	{ 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
> +	{ 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
> +	{ 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
> +	{ 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
> +};
> +
> +static const struct hwmon_channel_info *n5010bmc_hinfo[] = {
> +	HWMON_CHANNEL_INFO(temp,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL),
> +	HWMON_CHANNEL_INFO(in,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL),
> +	HWMON_CHANNEL_INFO(curr,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL),
> +	NULL
> +};
> +
> +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
> +	.tables = {
> +		[hwmon_temp] = n5010bmc_temp_tbl,
> +		[hwmon_in] = n5010bmc_in_tbl,
> +		[hwmon_curr] = n5010bmc_curr_tbl,
> +	},
> +
> +	.hinfo = n5010bmc_hinfo,
> +};
> +
>  static umode_t
>  m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
>  			u32 attr, int channel)
> @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
>  		.name = "d5005bmc-hwmon",
>  		.driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
>  	},
> +	{
> +		.name = "n5010bmc-hwmon",
> +		.driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
> +	},
>  	{ }
>  };
>  
> -- 
> 2.31.0

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-28  5:59   ` Xu Yilun
@ 2021-06-28 10:33     ` Lee Jones
  0 siblings, 0 replies; 25+ messages in thread
From: Lee Jones @ 2021-06-28 10:33 UTC (permalink / raw)
  To: Xu Yilun
  Cc: Martin Hundebøll, Wu Hao, Tom Rix, Moritz Fischer,
	Jean Delvare, Guenter Roeck, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Mon, 28 Jun 2021, Xu Yilun wrote:

> It is good to me.

Please provide a proper *-by tag:

  See the: 'Sign your work - the Developer's Certificate of Origin'
  section in Documentation/process/submitting-patches.rst

And please don't top post.

> On Fri, Jun 25, 2021 at 09:42:12AM +0200, Martin Hundebøll wrote:
> > From: Martin Hundebøll <mhu@silicom.dk>
> > 
> >  The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
> >  m10bmc types.
> > 
> > Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> > ---
> > 
> > Changes since v1:
> >  * Patch split out to separate mfd changes
> > 
> >  drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> > index 1a9bfb7f48cd..8db3bcf5fccc 100644
> > --- a/drivers/mfd/intel-m10-bmc.c
> > +++ b/drivers/mfd/intel-m10-bmc.c
> > @@ -15,7 +15,8 @@
> >  
> >  enum m10bmc_type {
> >  	M10_N3000,
> > -	M10_D5005
> > +	M10_D5005,
> > +	M10_N5010,
> >  };
> >  
> >  static struct mfd_cell m10bmc_d5005_subdevs[] = {
> > @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
> >  	{ .name = "n3000bmc-secure" },
> >  };
> >  
> > +static struct mfd_cell m10bmc_n5010_subdevs[] = {
> > +	{ .name = "n5010bmc-hwmon" },
> > +};
> > +
> >  static const struct regmap_range m10bmc_regmap_range[] = {
> >  	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
> >  	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
> > @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> >  		cells = m10bmc_d5005_subdevs;
> >  		n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
> >  		break;
> > +	case M10_N5010:
> > +		cells = m10bmc_n5010_subdevs;
> > +		n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
> > +		break;
> >  	default:
> >  		return -ENODEV;
> >  	}
> > @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> >  static const struct spi_device_id m10bmc_spi_id[] = {
> >  	{ "m10-n3000", M10_N3000 },
> >  	{ "m10-d5005", M10_D5005 },
> > +	{ "m10-n5010", M10_N5010 },
> >  	{ }
> >  };
> >  MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);

-- 
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-28  6:00   ` Xu Yilun
@ 2021-06-28 14:11     ` Guenter Roeck
  0 siblings, 0 replies; 25+ messages in thread
From: Guenter Roeck @ 2021-06-28 14:11 UTC (permalink / raw)
  To: Xu Yilun, Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Jean Delvare, Lee Jones,
	Mark Brown, Martin Hundebøll, linux-fpga, linux-kernel,
	linux-hwmon, linux-spi

On 6/27/21 11:00 PM, Xu Yilun wrote:
> It is good to me.
> 

As already pointed out, please don't top-post, and provide a
formal Reviewed-by: or Acked-by: tag.

Thanks,
Guenter

> On Fri, Jun 25, 2021 at 09:42:13AM +0200, Martin Hundebøll wrote:
>> From: Martin Hundebøll <mhu@silicom.dk>
>>
>> Add the list of sensors supported by the Silicom n5010 PAC, and enable
>> the drivers as a subtype of the intel-m10-bmc multi-function driver.
>>
>> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
>> ---
>>
>> Changes since v1:
>>   * Patch split out to separate hwmon changes
>>
>>   drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
>>   1 file changed, 116 insertions(+)
>>
>> diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
>> index bd7ed2ed3a1e..7a08e4c44a4b 100644
>> --- a/drivers/hwmon/intel-m10-bmc-hwmon.c
>> +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
>> @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
>>   	.hinfo = d5005bmc_hinfo,
>>   };
>>   
>> +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
>> +	{ 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
>> +	{ 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
>> +	{ 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
>> +	{ 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
>> +	{ 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
>> +	{ 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
>> +	{ 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
>> +	{ 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
>> +	{ 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
>> +	{ 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
>> +	{ 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
>> +	{ 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
>> +	{ 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
>> +	{ 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
>> +	{ 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
>> +	{ 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
>> +	{ 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
>> +};
>> +
>> +static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
>> +	{ 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
>> +	{ 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
>> +	{ 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
>> +	{ 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
>> +	{ 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
>> +	{ 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
>> +	{ 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
>> +	{ 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
>> +	{ 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
>> +	{ 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
>> +	{ 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
>> +	{ 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
>> +	{ 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
>> +};
>> +
>> +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
>> +	{ 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
>> +	{ 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
>> +	{ 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
>> +	{ 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
>> +	{ 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
>> +	{ 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
>> +	{ 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
>> +	{ 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
>> +	{ 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
>> +	{ 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
>> +	{ 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
>> +	{ 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
>> +	{ 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
>> +};
>> +
>> +static const struct hwmon_channel_info *n5010bmc_hinfo[] = {
>> +	HWMON_CHANNEL_INFO(temp,
>> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_INPUT | HWMON_T_LABEL),
>> +	HWMON_CHANNEL_INFO(in,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL,
>> +			   HWMON_I_INPUT | HWMON_I_LABEL),
>> +	HWMON_CHANNEL_INFO(curr,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL,
>> +			   HWMON_C_INPUT | HWMON_C_LABEL),
>> +	NULL
>> +};
>> +
>> +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
>> +	.tables = {
>> +		[hwmon_temp] = n5010bmc_temp_tbl,
>> +		[hwmon_in] = n5010bmc_in_tbl,
>> +		[hwmon_curr] = n5010bmc_curr_tbl,
>> +	},
>> +
>> +	.hinfo = n5010bmc_hinfo,
>> +};
>> +
>>   static umode_t
>>   m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
>>   			u32 attr, int channel)
>> @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
>>   		.name = "d5005bmc-hwmon",
>>   		.driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
>>   	},
>> +	{
>> +		.name = "n5010bmc-hwmon",
>> +		.driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
>> +	},
>>   	{ }
>>   };
>>   
>> -- 
>> 2.31.0


^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
  2021-06-28  6:00   ` Xu Yilun
@ 2021-06-28 16:35   ` Guenter Roeck
  2021-06-28 17:28     ` Moritz Fischer
  1 sibling, 1 reply; 25+ messages in thread
From: Guenter Roeck @ 2021-06-28 16:35 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Lee Jones, Mark Brown, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 09:42:13AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> Add the list of sensors supported by the Silicom n5010 PAC, and enable
> the drivers as a subtype of the intel-m10-bmc multi-function driver.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>

For my reference:

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

Not sure if I can apply this patch as-is to hwmon, or if it needs
to wait for the other patches in the series. Any thoughts / comments ?

Guenter

> ---
> 
> Changes since v1:
>  * Patch split out to separate hwmon changes
> 
>  drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c
> index bd7ed2ed3a1e..7a08e4c44a4b 100644
> --- a/drivers/hwmon/intel-m10-bmc-hwmon.c
> +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c
> @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {
>  	.hinfo = d5005bmc_hinfo,
>  };
>  
> +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {
> +	{ 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },
> +	{ 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },
> +	{ 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },
> +	{ 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },
> +	{ 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },
> +	{ 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },
> +	{ 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },
> +	{ 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },
> +	{ 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },
> +	{ 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },
> +	{ 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },
> +	{ 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },
> +	{ 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },
> +	{ 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },
> +	{ 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },
> +	{ 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },
> +	{ 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },
> +};
> +
> +static const struct m10bmc_sdata n5010bmc_in_tbl[] = {
> +	{ 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },
> +	{ 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },
> +	{ 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },
> +	{ 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },
> +	{ 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },
> +	{ 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },
> +	{ 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },
> +	{ 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },
> +	{ 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },
> +	{ 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },
> +	{ 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },
> +	{ 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },
> +	{ 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },
> +};
> +
> +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {
> +	{ 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },
> +	{ 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },
> +	{ 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },
> +	{ 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },
> +	{ 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },
> +	{ 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },
> +	{ 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },
> +	{ 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },
> +	{ 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },
> +	{ 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },
> +	{ 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },
> +	{ 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },
> +	{ 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },
> +};
> +
> +static const struct hwmon_channel_info *n5010bmc_hinfo[] = {
> +	HWMON_CHANNEL_INFO(temp,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_INPUT | HWMON_T_LABEL),
> +	HWMON_CHANNEL_INFO(in,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL,
> +			   HWMON_I_INPUT | HWMON_I_LABEL),
> +	HWMON_CHANNEL_INFO(curr,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL,
> +			   HWMON_C_INPUT | HWMON_C_LABEL),
> +	NULL
> +};
> +
> +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {
> +	.tables = {
> +		[hwmon_temp] = n5010bmc_temp_tbl,
> +		[hwmon_in] = n5010bmc_in_tbl,
> +		[hwmon_curr] = n5010bmc_curr_tbl,
> +	},
> +
> +	.hinfo = n5010bmc_hinfo,
> +};
> +
>  static umode_t
>  m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
>  			u32 attr, int channel)
> @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {
>  		.name = "d5005bmc-hwmon",
>  		.driver_data = (unsigned long)&d5005bmc_hwmon_bdata,
>  	},
> +	{
> +		.name = "n5010bmc-hwmon",
> +		.driver_data = (unsigned long)&n5010bmc_hwmon_bdata,
> +	},
>  	{ }
>  };
>  
> -- 
> 2.31.0
> 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-28 16:35   ` Guenter Roeck
@ 2021-06-28 17:28     ` Moritz Fischer
  2021-06-29  1:40       ` Xu Yilun
  0 siblings, 1 reply; 25+ messages in thread
From: Moritz Fischer @ 2021-06-28 17:28 UTC (permalink / raw)
  To: Guenter Roeck
  Cc: Martin Hundebøll, Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun,
	Jean Delvare, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

Hi Guenter,

On Mon, Jun 28, 2021 at 09:35:56AM -0700, Guenter Roeck wrote:
> On Fri, Jun 25, 2021 at 09:42:13AM +0200, Martin Hundebøll wrote:
> > From: Martin Hundebøll <mhu@silicom.dk>
> > 
> > Add the list of sensors supported by the Silicom n5010 PAC, and enable
> > the drivers as a subtype of the intel-m10-bmc multi-function driver.
> > 
> > Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> 
> For my reference:
> 
> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Moritz Fischer <mdf@kernel.org>

> 
> Not sure if I can apply this patch as-is to hwmon, or if it needs
> to wait for the other patches in the series. Any thoughts / comments ?

I don't see how it would break anything in itself since it just adds
extra compatible and data.

I'd probably wait with applying until discussions around the mfd and dfl
parts are resolved since otherwise there's no user.

> Guenter

Thanks,
Moritz

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
  2021-06-28  5:58   ` Xu Yilun
@ 2021-06-28 17:39   ` Moritz Fischer
  2021-06-29 11:35     ` Mark Brown
  2021-06-29 11:49     ` Martin Hundebøll
  1 sibling, 2 replies; 25+ messages in thread
From: Moritz Fischer @ 2021-06-28 17:39 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 09:42:11AM +0200, Martin Hundebøll wrote:
> From: Martin Hundebøll <mhu@silicom.dk>
> 
> The Max10 BMC on the Silicom n5010 PAC is slightly different than the
> existing BMC's, so use a dedicated feature revision detect it.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * use feature revision from struct dfl_device instead of reading it
>    from io-mem
> 
>  drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
> index 3e32e4fe5895..f6cf7c8d9dac 100644
> --- a/drivers/spi/spi-altera-dfl.c
> +++ b/drivers/spi/spi-altera-dfl.c
> @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
>  	.chip_select = 0,
>  };
>  
> +static struct spi_board_info m10_n5010_bmc_info = {
> +	.modalias = "m10-n5010",
> +	.max_speed_hz = 12500000,
> +	.bus_num = 0,
> +	.chip_select = 0,
> +};
Is there no way to query the mc for version info?
> +
>  static void config_spi_master(void __iomem *base, struct spi_master *master)
>  {
>  	u64 v;
> @@ -130,6 +137,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master)
>  
>  static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
>  {
> +	struct spi_board_info *board_info = &m10_bmc_info;
>  	struct device *dev = &dfl_dev->dev;
>  	struct spi_master *master;
>  	struct altera_spi *hw;
> @@ -172,9 +180,12 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
>  		goto exit;
>  	}
>  
> -	if (!spi_new_device(master,  &m10_bmc_info)) {
> +	if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010)
> +		board_info = &m10_n5010_bmc_info;

Since this depends on the previous patch: Mark do you want to take both
patches once they're reviewed? From what I can tell the BMC and HWMON
don't directly depend on it, so taking them through SPI tree might be
easiest.

Alternatively I can provide a tag for the DFL change for you to pull.

> +
> +	if (!spi_new_device(master, board_info)) {
>  		dev_err(dev, "%s failed to create SPI device: %s\n",
> -			__func__, m10_bmc_info.modalias);
> +			__func__, board_info->modalias);
>  	}
>  
>  	return 0;
> -- 
> 2.31.0
> 

- Moritz

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-25 18:45   ` Moritz Fischer
@ 2021-06-29  1:39     ` Xu Yilun
  0 siblings, 0 replies; 25+ messages in thread
From: Xu Yilun @ 2021-06-29  1:39 UTC (permalink / raw)
  To: Moritz Fischer
  Cc: Martin Hundebøll, Wu Hao, Tom Rix, Jean Delvare,
	Guenter Roeck, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Fri, Jun 25, 2021 at 11:45:49AM -0700, Moritz Fischer wrote:
> On Fri, Jun 25, 2021 at 09:42:12AM +0200, Martin Hundebøll wrote:
> > From: Martin Hundebøll <mhu@silicom.dk>
> > 
> >  The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
> >  m10bmc types.
> > 
> > Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> Acked-by: Moritz Fischer <mdf@kernel.org>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>

Thanks,
Yilun

> > ---
> > 
> > Changes since v1:
> >  * Patch split out to separate mfd changes
> > 
> >  drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c
> > index 1a9bfb7f48cd..8db3bcf5fccc 100644
> > --- a/drivers/mfd/intel-m10-bmc.c
> > +++ b/drivers/mfd/intel-m10-bmc.c
> > @@ -15,7 +15,8 @@
> >  
> >  enum m10bmc_type {
> >  	M10_N3000,
> > -	M10_D5005
> > +	M10_D5005,
> > +	M10_N5010,
> >  };
> >  
> >  static struct mfd_cell m10bmc_d5005_subdevs[] = {
> > @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
> >  	{ .name = "n3000bmc-secure" },
> >  };
> >  
> > +static struct mfd_cell m10bmc_n5010_subdevs[] = {
> > +	{ .name = "n5010bmc-hwmon" },
> > +};
> > +
> >  static const struct regmap_range m10bmc_regmap_range[] = {
> >  	regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
> >  	regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
> > @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> >  		cells = m10bmc_d5005_subdevs;
> >  		n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs);
> >  		break;
> > +	case M10_N5010:
> > +		cells = m10bmc_n5010_subdevs;
> > +		n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs);
> > +		break;
> >  	default:
> >  		return -ENODEV;
> >  	}
> > @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
> >  static const struct spi_device_id m10bmc_spi_id[] = {
> >  	{ "m10-n3000", M10_N3000 },
> >  	{ "m10-d5005", M10_D5005 },
> > +	{ "m10-n5010", M10_N5010 },
> >  	{ }
> >  };
> >  MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
> > -- 
> > 2.31.0
> > 

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors
  2021-06-28 17:28     ` Moritz Fischer
@ 2021-06-29  1:40       ` Xu Yilun
  0 siblings, 0 replies; 25+ messages in thread
From: Xu Yilun @ 2021-06-29  1:40 UTC (permalink / raw)
  To: Moritz Fischer
  Cc: Guenter Roeck, Martin Hundebøll, Wu Hao, Tom Rix,
	Jean Delvare, Lee Jones, Mark Brown, Martin Hundebøll,
	linux-fpga, linux-kernel, linux-hwmon, linux-spi

On Mon, Jun 28, 2021 at 10:28:28AM -0700, Moritz Fischer wrote:
> Hi Guenter,
> 
> On Mon, Jun 28, 2021 at 09:35:56AM -0700, Guenter Roeck wrote:
> > On Fri, Jun 25, 2021 at 09:42:13AM +0200, Martin Hundebøll wrote:
> > > From: Martin Hundebøll <mhu@silicom.dk>
> > > 
> > > Add the list of sensors supported by the Silicom n5010 PAC, and enable
> > > the drivers as a subtype of the intel-m10-bmc multi-function driver.
> > > 
> > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> > 
> > For my reference:
> > 
> > Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Moritz Fischer <mdf@kernel.org>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>

Thanks,
Yilun

> 
> > 
> > Not sure if I can apply this patch as-is to hwmon, or if it needs
> > to wait for the other patches in the series. Any thoughts / comments ?
> 
> I don't see how it would break anything in itself since it just adds
> extra compatible and data.
> 
> I'd probably wait with applying until discussions around the mfd and dfl
> parts are resolved since otherwise there's no user.
> 
> > Guenter
> 
> Thanks,
> Moritz

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-28 17:39   ` Moritz Fischer
@ 2021-06-29 11:35     ` Mark Brown
  2021-06-29 11:49     ` Martin Hundebøll
  1 sibling, 0 replies; 25+ messages in thread
From: Mark Brown @ 2021-06-29 11:35 UTC (permalink / raw)
  To: Moritz Fischer
  Cc: Martin Hundebøll, Wu Hao, Tom Rix, Xu Yilun, Jean Delvare,
	Guenter Roeck, Lee Jones, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

[-- Attachment #1: Type: text/plain, Size: 442 bytes --]

On Mon, Jun 28, 2021 at 10:39:23AM -0700, Moritz Fischer wrote:

> Since this depends on the previous patch: Mark do you want to take both
> patches once they're reviewed? From what I can tell the BMC and HWMON
> don't directly depend on it, so taking them through SPI tree might be
> easiest.

> Alternatively I can provide a tag for the DFL change for you to pull.

Sure, I can do whichever - I guess me applying both is probably
simplest?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-28 17:39   ` Moritz Fischer
  2021-06-29 11:35     ` Mark Brown
@ 2021-06-29 11:49     ` Martin Hundebøll
  2021-06-29 14:37       ` Wu, Hao
  1 sibling, 1 reply; 25+ messages in thread
From: Martin Hundebøll @ 2021-06-29 11:49 UTC (permalink / raw)
  To: Moritz Fischer, Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Xu Yilun, Jean Delvare, Guenter Roeck,
	Lee Jones, Mark Brown, linux-fpga, linux-kernel, linux-hwmon,
	linux-spi

On 28/06/2021 19.39, Moritz Fischer wrote:
> On Fri, Jun 25, 2021 at 09:42:11AM +0200, Martin Hundebøll wrote:
>> From: Martin Hundebøll<mhu@silicom.dk>
>>
>> The Max10 BMC on the Silicom n5010 PAC is slightly different than the
>> existing BMC's, so use a dedicated feature revision detect it.
>>
>> Signed-off-by: Martin Hundebøll<mhu@silicom.dk>
>> ---
>>
>> Changes since v1:
>>   * use feature revision from struct dfl_device instead of reading it
>>     from io-mem
>>
>>   drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
>>   1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
>> index 3e32e4fe5895..f6cf7c8d9dac 100644
>> --- a/drivers/spi/spi-altera-dfl.c
>> +++ b/drivers/spi/spi-altera-dfl.c
>> @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
>>   	.chip_select = 0,
>>   };
>>   
>> +static struct spi_board_info m10_n5010_bmc_info = {
>> +	.modalias = "m10-n5010",
>> +	.max_speed_hz = 12500000,
>> +	.bus_num = 0,
>> +	.chip_select = 0,
>> +};
> Is there no way to query the mc for version info?

Do you mean reading the BMC variant (i.e. n5010 / d5005 / n3000) from a
register?

Not in a uniform way across the different boards that I'm aware of. But
isn't this what the DFL feature revision is meant for?

// Martin

^ permalink raw reply	[flat|nested] 25+ messages in thread

* RE: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-29 11:49     ` Martin Hundebøll
@ 2021-06-29 14:37       ` Wu, Hao
  2021-06-29 22:30         ` matthew.gerlach
  0 siblings, 1 reply; 25+ messages in thread
From: Wu, Hao @ 2021-06-29 14:37 UTC (permalink / raw)
  To: Martin Hundebøll, Moritz Fischer, Martin Hundebøll
  Cc: Tom Rix, Xu, Yilun, Jean Delvare, Guenter Roeck, Lee Jones,
	Mark Brown, linux-fpga, linux-kernel, linux-hwmon, linux-spi

> On 28/06/2021 19.39, Moritz Fischer wrote:
> > On Fri, Jun 25, 2021 at 09:42:11AM +0200, Martin Hundebøll wrote:
> >> From: Martin Hundebøll<mhu@silicom.dk>
> >>
> >> The Max10 BMC on the Silicom n5010 PAC is slightly different than the
> >> existing BMC's, so use a dedicated feature revision detect it.
> >>
> >> Signed-off-by: Martin Hundebøll<mhu@silicom.dk>
> >> ---
> >>
> >> Changes since v1:
> >>   * use feature revision from struct dfl_device instead of reading it
> >>     from io-mem
> >>
> >>   drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
> >>   1 file changed, 13 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
> >> index 3e32e4fe5895..f6cf7c8d9dac 100644
> >> --- a/drivers/spi/spi-altera-dfl.c
> >> +++ b/drivers/spi/spi-altera-dfl.c
> >> @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
> >>   	.chip_select = 0,
> >>   };
> >>
> >> +static struct spi_board_info m10_n5010_bmc_info = {
> >> +	.modalias = "m10-n5010",
> >> +	.max_speed_hz = 12500000,
> >> +	.bus_num = 0,
> >> +	.chip_select = 0,
> >> +};
> > Is there no way to query the mc for version info?
> 
> Do you mean reading the BMC variant (i.e. n5010 / d5005 / n3000) from a
> register?
> 
> Not in a uniform way across the different boards that I'm aware of. But
> isn't this what the DFL feature revision is meant for?

If this is used to distinguish different boards, then revision (4bits?) may not
be enough. New version DFH may be able to resolve this limitation, but it
is always encouraged to have its own method to tell if possible, not depending
on DFH, it makes this IP easy to be reused in non DFL case. 

Thanks
Hao

> 
> // Martin

^ permalink raw reply	[flat|nested] 25+ messages in thread

* RE: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision
  2021-06-29 14:37       ` Wu, Hao
@ 2021-06-29 22:30         ` matthew.gerlach
  0 siblings, 0 replies; 25+ messages in thread
From: matthew.gerlach @ 2021-06-29 22:30 UTC (permalink / raw)
  To: Wu, Hao
  Cc: Martin Hundebøll, Moritz Fischer, Martin Hundebøll,
	Tom Rix, Xu, Yilun, Jean Delvare, Guenter Roeck, Lee Jones,
	Mark Brown, linux-fpga, linux-kernel, linux-hwmon, linux-spi

[-- Attachment #1: Type: text/plain, Size: 2509 bytes --]



On Tue, 29 Jun 2021, Wu, Hao wrote:

>> On 28/06/2021 19.39, Moritz Fischer wrote:
>>> On Fri, Jun 25, 2021 at 09:42:11AM +0200, Martin Hundebøll wrote:
>>>> From: Martin Hundebøll<mhu@silicom.dk>
>>>>
>>>> The Max10 BMC on the Silicom n5010 PAC is slightly different than the
>>>> existing BMC's, so use a dedicated feature revision detect it.
>>>>
>>>> Signed-off-by: Martin Hundebøll<mhu@silicom.dk>
>>>> ---
>>>>
>>>> Changes since v1:
>>>>   * use feature revision from struct dfl_device instead of reading it
>>>>     from io-mem
>>>>
>>>>   drivers/spi/spi-altera-dfl.c | 15 +++++++++++++--
>>>>   1 file changed, 13 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c
>>>> index 3e32e4fe5895..f6cf7c8d9dac 100644
>>>> --- a/drivers/spi/spi-altera-dfl.c
>>>> +++ b/drivers/spi/spi-altera-dfl.c
>>>> @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = {
>>>>   	.chip_select = 0,
>>>>   };
>>>>
>>>> +static struct spi_board_info m10_n5010_bmc_info = {
>>>> +	.modalias = "m10-n5010",
>>>> +	.max_speed_hz = 12500000,
>>>> +	.bus_num = 0,
>>>> +	.chip_select = 0,
>>>> +};
>>> Is there no way to query the mc for version info?
>>
>> Do you mean reading the BMC variant (i.e. n5010 / d5005 / n3000) from a
>> register?
>>
>> Not in a uniform way across the different boards that I'm aware of. But
>> isn't this what the DFL feature revision is meant for?
>
> If this is used to distinguish different boards, then revision (4bits?) may not

On the one hand, the revision is being used to distinguish the board. 
More precisely, the feature ID id determining the actual hardware 
involved, altera-spi connected to a particular indirect register mailbox. 
This is a different feature id used by the n3000 which has a different 
indirect register mailbox with a NIOS hanshake.  So in this case the revision
is being used to specify remote end of the SPI connection, d5005 BMC vs. 
n5010 BMC.

I think in this case 4 bits is enough.  We've only had two instances 
of this hardware in 5 years.  Certainly any future instances of this
hardware should have a register describing the remote end of the SPI 
connection.  This hardware change would then require a new feature id.

> be enough. New version DFH may be able to resolve this limitation, but it
> is always encouraged to have its own method to tell if possible, not depending
> on DFH, it makes this IP easy to be reused in non DFL case.
>
> Thanks
> Hao
>
>>
>> // Martin
>

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant
  2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
  2021-06-25 18:45   ` Moritz Fischer
  2021-06-28  5:59   ` Xu Yilun
@ 2021-06-30 10:57   ` Lee Jones
  2 siblings, 0 replies; 25+ messages in thread
From: Lee Jones @ 2021-06-30 10:57 UTC (permalink / raw)
  To: Martin Hundebøll
  Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
	Guenter Roeck, Mark Brown, Martin Hundebøll, linux-fpga,
	linux-kernel, linux-hwmon, linux-spi

On Fri, 25 Jun 2021, Martin Hundebøll wrote:

> From: Martin Hundebøll <mhu@silicom.dk>
> 
>  The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of
>  m10bmc types.
> 
> Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
> ---
> 
> Changes since v1:
>  * Patch split out to separate mfd changes
> 
>  drivers/mfd/intel-m10-bmc.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)

For my own reference (apply this as-is to your sign-off block):

  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>

-- 
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2021-06-30 10:57 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
2021-06-25  7:42 ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Martin Hundebøll
2021-06-25 18:43   ` Moritz Fischer
2021-06-25  7:42 ` [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
2021-06-25 19:26   ` Moritz Fischer
2021-06-28  3:38     ` Wu, Hao
2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
2021-06-28  5:58   ` Xu Yilun
2021-06-28 17:39   ` Moritz Fischer
2021-06-29 11:35     ` Mark Brown
2021-06-29 11:49     ` Martin Hundebøll
2021-06-29 14:37       ` Wu, Hao
2021-06-29 22:30         ` matthew.gerlach
2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
2021-06-25 18:45   ` Moritz Fischer
2021-06-29  1:39     ` Xu Yilun
2021-06-28  5:59   ` Xu Yilun
2021-06-28 10:33     ` Lee Jones
2021-06-30 10:57   ` Lee Jones
2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
2021-06-28  6:00   ` Xu Yilun
2021-06-28 14:11     ` Guenter Roeck
2021-06-28 16:35   ` Guenter Roeck
2021-06-28 17:28     ` Moritz Fischer
2021-06-29  1:40       ` Xu Yilun

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