* [PATCH v5 0/3] fpga/spi/hwmon: Initial support for Silicom N5010 PAC
@ 2021-07-16 13:54 Martin Hundebøll
2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Martin Hundebøll @ 2021-07-16 13:54 UTC (permalink / raw)
To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare,
Guenter Roeck, Mark Brown
Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi
From: Martin Hundebøll <mhu@silicom.dk>
This is an initial set of patches for the Silciom N5010 programmable
accelerated card adding support for reading out sensors.
Based on v5.14-rc1
Changes since v4:
* Removed the mfd patch that has been applied by Lee
* Renamed 'rev' to 'revision' in patch 1/3 as per Tom's suggestion
* Moved spi board_info structure in patch 2/3 from global/static scope
to function/stack scope
Changes since v3:
* Added Hao's Acked-by to patch 1/4
* Added Matthew's Acked-by to patch 1/4
* Changed "BMC's" to "BMCs" in patch 2/4
* Added Moritz' Reviewed-by to patch 2/4
* Added Matthew's Reviewed-by to patch 3/4
* Added Lee's Acked-for-MFD-by to patch 3/4
Changes since v2:
* Removed patch 1/5 from v2 already in fpga/for-next
* Reworded commit message in patch 1/4 as per Hao's suggestion
* Added Yilun's Reviewed-by to patch 3/4 and 4/4
* Added Moritz' Acked-by to patch 3/4
* Added Moritz' Reviewed-by to patch 4/4
* Added Guenter's Reviewed-by to patch 4/4
Changes since v1:
* Commit message in patch 1 is updated with card description
* Added Hao's Acked-by to patch 1
* Patch 2 is replaced with a new patch to carry feature revision info
in struct dfl_device
* Patch 3 is updated to use feature revision from struct dfl_device
* Patch 4 from v0 is split into separate patches for hwmon and mfd
Martin Hundebøll (3):
fpga: dfl: expose feature revision from struct dfl_device
spi: spi-altera-dfl: support n5010 feature revision
hwmon: intel-m10-bmc-hwmon: add n5010 sensors
drivers/fpga/dfl.c | 27 ++++---
drivers/fpga/dfl.h | 1 +
drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++
drivers/spi/spi-altera-dfl.c | 21 ++---
include/linux/dfl.h | 1 +
5 files changed, 147 insertions(+), 19 deletions(-)
--
2.31.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device 2021-07-16 13:54 [PATCH v5 0/3] fpga/spi/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll @ 2021-07-16 13:54 ` Martin Hundebøll 2021-07-16 20:46 ` Tom Rix 2021-07-29 20:04 ` Moritz Fischer 2021-07-16 13:54 ` [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll 2021-07-16 13:54 ` [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll 2 siblings, 2 replies; 11+ messages in thread From: Martin Hundebøll @ 2021-07-16 13:54 UTC (permalink / raw) To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi, Matthew Gerlach From: Martin Hundebøll <mhu@silicom.dk> DFL device drivers have a common need for checking feature revision information from the DFL header, as well as other common DFL information like the already exposed feature id and type. This patch exposes the feature revision information directly via the DFL device data structure. Since the DFL core code has already read the DFL header, this this patch saves additional mmio reads from DFL device drivers too. Signed-off-by: Martin Hundebøll <mhu@silicom.dk> Acked-by: Wu Hao <hao.wu@intel.com> Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- Changes since v4: * Renamed 'rev' to 'revision' as per Tom's suggestion Changes since v3: * Added Hao's Acked-by * Added Matthew's Acked-by Changes since v2: * Reworded commit message as per Hao's suggestion Changes since v1: * This patch replaces the previous patch 2 and exposes the feature revision through struct dfl_device instead of a helper reading from io-mem drivers/fpga/dfl.c | 27 +++++++++++++++++---------- drivers/fpga/dfl.h | 1 + include/linux/dfl.h | 1 + 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 511b20ff35a3..e73a70053906 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; + ddev->revision = feature->revision; ddev->cdev = pdata->dfl_cdev; /* add mmio resource */ @@ -717,6 +718,7 @@ struct build_feature_devs_info { */ struct dfl_feature_info { u16 fid; + u8 revision; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) /* save resource information for each feature */ feature->dev = fdev; feature->id = finfo->fid; + feature->revision = finfo->revision; /* * the FIU header feature has some fundamental functions (sriov @@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo) devm_kfree(binfo->dev, binfo); } -static inline u32 feature_size(void __iomem *start) +static inline u32 feature_size(u64 value) { - u64 v = readq(start + DFH); - u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v); + u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value); /* workaround for private features with invalid size, use 4K instead */ return ofst ? ofst : 4096; } -static u16 feature_id(void __iomem *start) +static u16 feature_id(u64 value) { - u64 v = readq(start + DFH); - u16 id = FIELD_GET(DFH_ID, v); - u8 type = FIELD_GET(DFH_TYPE, v); + u16 id = FIELD_GET(DFH_ID, value); + u8 type = FIELD_GET(DFH_TYPE, value); if (type == DFH_TYPE_FIU) return FEATURE_ID_FIU_HEADER; @@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo, unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; int ret; + u8 revision; + u64 v; + + v = readq(binfo->ioaddr + ofst); + revision = FIELD_GET(DFH_REVISION, v); /* read feature size and id if inputs are invalid */ - size = size ? size : feature_size(binfo->ioaddr + ofst); - fid = fid ? fid : feature_id(binfo->ioaddr + ofst); + size = size ? size : feature_size(v); + fid = fid ? fid : feature_id(v); if (binfo->len - ofst < size) return -EINVAL; @@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, return -ENOMEM; finfo->fid = fid; + finfo->revision = revision; finfo->mmio_res.start = binfo->start + ofst; finfo->mmio_res.end = finfo->mmio_res.start + size - 1; finfo->mmio_res.flags = IORESOURCE_MEM; @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo, { if (!is_feature_dev_detected(binfo)) { dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n", - feature_id(binfo->ioaddr + ofst)); + feature_id(readq(binfo->ioaddr + ofst))); return -EINVAL; } diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 2b82c96ba56c..422157cfd742 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx { struct dfl_feature { struct platform_device *dev; u16 id; + u8 revision; int resource_index; void __iomem *ioaddr; struct dfl_feature_irq_ctx *irq_ctx; diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 6cc10982351a..431636a0dc78 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -38,6 +38,7 @@ struct dfl_device { int id; u16 type; u16 feature_id; + u8 revision; struct resource mmio_res; int *irqs; unsigned int num_irqs; -- 2.31.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device 2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll @ 2021-07-16 20:46 ` Tom Rix 2021-07-29 20:04 ` Moritz Fischer 1 sibling, 0 replies; 11+ messages in thread From: Tom Rix @ 2021-07-16 20:46 UTC (permalink / raw) To: Martin Hundebøll, Wu Hao, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi, Matthew Gerlach On 7/16/21 6:54 AM, Martin Hundebøll wrote: > From: Martin Hundebøll <mhu@silicom.dk> > > DFL device drivers have a common need for checking feature revision > information from the DFL header, as well as other common DFL information > like the already exposed feature id and type. > > This patch exposes the feature revision information directly via the DFL > device data structure. > > Since the DFL core code has already read the DFL header, this this patch > saves additional mmio reads from DFL device drivers too. > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk> > Acked-by: Wu Hao <hao.wu@intel.com> > Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > --- > > Changes since v4: > * Renamed 'rev' to 'revision' as per Tom's suggestion > > Changes since v3: > * Added Hao's Acked-by > * Added Matthew's Acked-by > > Changes since v2: > * Reworded commit message as per Hao's suggestion > > Changes since v1: > * This patch replaces the previous patch 2 and exposes the feature > revision through struct dfl_device instead of a helper reading from > io-mem > > drivers/fpga/dfl.c | 27 +++++++++++++++++---------- > drivers/fpga/dfl.h | 1 + > include/linux/dfl.h | 1 + > 3 files changed, 19 insertions(+), 10 deletions(-) > > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c > index 511b20ff35a3..e73a70053906 100644 > --- a/drivers/fpga/dfl.c > +++ b/drivers/fpga/dfl.c > @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, > > ddev->type = feature_dev_id_type(pdev); > ddev->feature_id = feature->id; > + ddev->revision = feature->revision; > ddev->cdev = pdata->dfl_cdev; > > /* add mmio resource */ > @@ -717,6 +718,7 @@ struct build_feature_devs_info { > */ > struct dfl_feature_info { > u16 fid; > + u8 revision; > struct resource mmio_res; > void __iomem *ioaddr; > struct list_head node; > @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) > /* save resource information for each feature */ > feature->dev = fdev; > feature->id = finfo->fid; > + feature->revision = finfo->revision; > > /* > * the FIU header feature has some fundamental functions (sriov > @@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo) > devm_kfree(binfo->dev, binfo); > } > > -static inline u32 feature_size(void __iomem *start) > +static inline u32 feature_size(u64 value) > { > - u64 v = readq(start + DFH); > - u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v); > + u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value); > /* workaround for private features with invalid size, use 4K instead */ > return ofst ? ofst : 4096; > } > > -static u16 feature_id(void __iomem *start) > +static u16 feature_id(u64 value) > { > - u64 v = readq(start + DFH); > - u16 id = FIELD_GET(DFH_ID, v); > - u8 type = FIELD_GET(DFH_TYPE, v); > + u16 id = FIELD_GET(DFH_ID, value); > + u8 type = FIELD_GET(DFH_TYPE, value); > > if (type == DFH_TYPE_FIU) > return FEATURE_ID_FIU_HEADER; > @@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo, > unsigned int irq_base, nr_irqs; > struct dfl_feature_info *finfo; > int ret; > + u8 revision; > + u64 v; > + > + v = readq(binfo->ioaddr + ofst); > + revision = FIELD_GET(DFH_REVISION, v); > > /* read feature size and id if inputs are invalid */ > - size = size ? size : feature_size(binfo->ioaddr + ofst); > - fid = fid ? fid : feature_id(binfo->ioaddr + ofst); > + size = size ? size : feature_size(v); > + fid = fid ? fid : feature_id(v); > > if (binfo->len - ofst < size) > return -EINVAL; > @@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, > return -ENOMEM; > > finfo->fid = fid; > + finfo->revision = revision; > finfo->mmio_res.start = binfo->start + ofst; > finfo->mmio_res.end = finfo->mmio_res.start + size - 1; > finfo->mmio_res.flags = IORESOURCE_MEM; > @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo, > { > if (!is_feature_dev_detected(binfo)) { > dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n", > - feature_id(binfo->ioaddr + ofst)); > + feature_id(readq(binfo->ioaddr + ofst))); > return -EINVAL; > } > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > index 2b82c96ba56c..422157cfd742 100644 > --- a/drivers/fpga/dfl.h > +++ b/drivers/fpga/dfl.h > @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx { > struct dfl_feature { > struct platform_device *dev; > u16 id; > + u8 revision; > int resource_index; > void __iomem *ioaddr; > struct dfl_feature_irq_ctx *irq_ctx; > diff --git a/include/linux/dfl.h b/include/linux/dfl.h > index 6cc10982351a..431636a0dc78 100644 > --- a/include/linux/dfl.h > +++ b/include/linux/dfl.h > @@ -38,6 +38,7 @@ struct dfl_device { > int id; > u16 type; > u16 feature_id; > + u8 revision; > struct resource mmio_res; > int *irqs; > unsigned int num_irqs; Looks good to me. Reviewed-by: Tom Rix <trix@redhat.com> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device 2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll 2021-07-16 20:46 ` Tom Rix @ 2021-07-29 20:04 ` Moritz Fischer 1 sibling, 0 replies; 11+ messages in thread From: Moritz Fischer @ 2021-07-29 20:04 UTC (permalink / raw) To: Martin Hundebøll Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown, Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi, Matthew Gerlach On Fri, Jul 16, 2021 at 03:54:39PM +0200, Martin Hundebøll wrote: > From: Martin Hundebøll <mhu@silicom.dk> > > DFL device drivers have a common need for checking feature revision > information from the DFL header, as well as other common DFL information > like the already exposed feature id and type. > > This patch exposes the feature revision information directly via the DFL > device data structure. > > Since the DFL core code has already read the DFL header, this this patch > saves additional mmio reads from DFL device drivers too. > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk> > Acked-by: Wu Hao <hao.wu@intel.com> > Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > --- > > Changes since v4: > * Renamed 'rev' to 'revision' as per Tom's suggestion > > Changes since v3: > * Added Hao's Acked-by > * Added Matthew's Acked-by > > Changes since v2: > * Reworded commit message as per Hao's suggestion > > Changes since v1: > * This patch replaces the previous patch 2 and exposes the feature > revision through struct dfl_device instead of a helper reading from > io-mem > > drivers/fpga/dfl.c | 27 +++++++++++++++++---------- > drivers/fpga/dfl.h | 1 + > include/linux/dfl.h | 1 + > 3 files changed, 19 insertions(+), 10 deletions(-) > > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c > index 511b20ff35a3..e73a70053906 100644 > --- a/drivers/fpga/dfl.c > +++ b/drivers/fpga/dfl.c > @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, > > ddev->type = feature_dev_id_type(pdev); > ddev->feature_id = feature->id; > + ddev->revision = feature->revision; > ddev->cdev = pdata->dfl_cdev; > > /* add mmio resource */ > @@ -717,6 +718,7 @@ struct build_feature_devs_info { > */ > struct dfl_feature_info { > u16 fid; > + u8 revision; > struct resource mmio_res; > void __iomem *ioaddr; > struct list_head node; > @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) > /* save resource information for each feature */ > feature->dev = fdev; > feature->id = finfo->fid; > + feature->revision = finfo->revision; > > /* > * the FIU header feature has some fundamental functions (sriov > @@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo) > devm_kfree(binfo->dev, binfo); > } > > -static inline u32 feature_size(void __iomem *start) > +static inline u32 feature_size(u64 value) > { > - u64 v = readq(start + DFH); > - u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v); > + u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value); > /* workaround for private features with invalid size, use 4K instead */ > return ofst ? ofst : 4096; > } > > -static u16 feature_id(void __iomem *start) > +static u16 feature_id(u64 value) > { > - u64 v = readq(start + DFH); > - u16 id = FIELD_GET(DFH_ID, v); > - u8 type = FIELD_GET(DFH_TYPE, v); > + u16 id = FIELD_GET(DFH_ID, value); > + u8 type = FIELD_GET(DFH_TYPE, value); > > if (type == DFH_TYPE_FIU) > return FEATURE_ID_FIU_HEADER; > @@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo, > unsigned int irq_base, nr_irqs; > struct dfl_feature_info *finfo; > int ret; > + u8 revision; > + u64 v; > + > + v = readq(binfo->ioaddr + ofst); > + revision = FIELD_GET(DFH_REVISION, v); > > /* read feature size and id if inputs are invalid */ > - size = size ? size : feature_size(binfo->ioaddr + ofst); > - fid = fid ? fid : feature_id(binfo->ioaddr + ofst); > + size = size ? size : feature_size(v); > + fid = fid ? fid : feature_id(v); > > if (binfo->len - ofst < size) > return -EINVAL; > @@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, > return -ENOMEM; > > finfo->fid = fid; > + finfo->revision = revision; > finfo->mmio_res.start = binfo->start + ofst; > finfo->mmio_res.end = finfo->mmio_res.start + size - 1; > finfo->mmio_res.flags = IORESOURCE_MEM; > @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo, > { > if (!is_feature_dev_detected(binfo)) { > dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n", > - feature_id(binfo->ioaddr + ofst)); > + feature_id(readq(binfo->ioaddr + ofst))); > return -EINVAL; > } > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > index 2b82c96ba56c..422157cfd742 100644 > --- a/drivers/fpga/dfl.h > +++ b/drivers/fpga/dfl.h > @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx { > struct dfl_feature { > struct platform_device *dev; > u16 id; > + u8 revision; > int resource_index; > void __iomem *ioaddr; > struct dfl_feature_irq_ctx *irq_ctx; > diff --git a/include/linux/dfl.h b/include/linux/dfl.h > index 6cc10982351a..431636a0dc78 100644 > --- a/include/linux/dfl.h > +++ b/include/linux/dfl.h > @@ -38,6 +38,7 @@ struct dfl_device { > int id; > u16 type; > u16 feature_id; > + u8 revision; > struct resource mmio_res; > int *irqs; > unsigned int num_irqs; > -- > 2.31.0 > Applied to for-next, Thanks ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision 2021-07-16 13:54 [PATCH v5 0/3] fpga/spi/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll 2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll @ 2021-07-16 13:54 ` Martin Hundebøll 2021-07-16 17:33 ` Mark Brown 2021-07-16 20:44 ` Tom Rix 2021-07-16 13:54 ` [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll 2 siblings, 2 replies; 11+ messages in thread From: Martin Hundebøll @ 2021-07-16 13:54 UTC (permalink / raw) To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi From: Martin Hundebøll <mhu@silicom.dk> The Max10 BMC on the Silicom n5010 PAC is slightly different than the existing BMCs, so use a dedicated feature revision detect it. Signed-off-by: Martin Hundebøll <mhu@silicom.dk> Reviewed-by: Moritz Fischer <mdf@kernel.org> --- Changes since v4: * Moved spi board_info structure from global/static scope to function/stack scope Changes since v3: * Changed "BMC's" to "BMCs" * Added Moritz' Reviewed-by Changes since v2: * None Changes since v1: * use feature revision from struct dfl_device instead of reading it from io-mem drivers/spi/spi-altera-dfl.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c index 39a3e1a032e0..44fc9ee13fc7 100644 --- a/drivers/spi/spi-altera-dfl.c +++ b/drivers/spi/spi-altera-dfl.c @@ -104,13 +104,6 @@ static const struct regmap_config indirect_regbus_cfg = { .reg_read = indirect_bus_reg_read, }; -static struct spi_board_info m10_bmc_info = { - .modalias = "m10-d5005", - .max_speed_hz = 12500000, - .bus_num = 0, - .chip_select = 0, -}; - static void config_spi_master(void __iomem *base, struct spi_master *master) { u64 v; @@ -130,6 +123,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master) static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) { + struct spi_board_info board_info = { 0 }; struct device *dev = &dfl_dev->dev; struct spi_master *master; struct altera_spi *hw; @@ -170,9 +164,18 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) goto exit; } - if (!spi_new_device(master, &m10_bmc_info)) { + if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010) + strscpy(board_info.modalias, "m10-n5010", SPI_NAME_SIZE); + else + strscpy(board_info.modalias, "m10-d5005", SPI_NAME_SIZE); + + board_info.max_speed_hz = 12500000; + board_info.bus_num = 0; + board_info.chip_select = 0; + + if (!spi_new_device(master, &board_info)) { dev_err(dev, "%s failed to create SPI device: %s\n", - __func__, m10_bmc_info.modalias); + __func__, board_info.modalias); } return 0; -- 2.31.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision 2021-07-16 13:54 ` [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll @ 2021-07-16 17:33 ` Mark Brown 2021-07-17 23:56 ` Moritz Fischer 2021-07-16 20:44 ` Tom Rix 1 sibling, 1 reply; 11+ messages in thread From: Mark Brown @ 2021-07-16 17:33 UTC (permalink / raw) To: Martin Hundebøll Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi [-- Attachment #1: Type: text/plain, Size: 297 bytes --] On Fri, Jul 16, 2021 at 03:54:40PM +0200, Martin Hundebøll wrote: > From: Martin Hundebøll <mhu@silicom.dk> > > The Max10 BMC on the Silicom n5010 PAC is slightly different than the > existing BMCs, so use a dedicated feature revision detect it. Acked-by: Mark Brown <broonie@kernel.org> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision 2021-07-16 17:33 ` Mark Brown @ 2021-07-17 23:56 ` Moritz Fischer 0 siblings, 0 replies; 11+ messages in thread From: Moritz Fischer @ 2021-07-17 23:56 UTC (permalink / raw) To: Mark Brown Cc: Martin Hundebøll, Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi On Fri, Jul 16, 2021 at 06:33:35PM +0100, Mark Brown wrote: > On Fri, Jul 16, 2021 at 03:54:40PM +0200, Martin Hundebøll wrote: > > From: Martin Hundebøll <mhu@silicom.dk> > > > > The Max10 BMC on the Silicom n5010 PAC is slightly different than the > > existing BMCs, so use a dedicated feature revision detect it. > > Acked-by: Mark Brown <broonie@kernel.org> Mark do you want me to provide a tag for this and the previous commit to avoid conflicts for other FPGA changes or do you think it's easier to just pick both of them up through FPGA or SPI tree? - Moritz ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision 2021-07-16 13:54 ` [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll 2021-07-16 17:33 ` Mark Brown @ 2021-07-16 20:44 ` Tom Rix 2021-07-29 20:05 ` Moritz Fischer 1 sibling, 1 reply; 11+ messages in thread From: Tom Rix @ 2021-07-16 20:44 UTC (permalink / raw) To: Martin Hundebøll, Wu Hao, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi On 7/16/21 6:54 AM, Martin Hundebøll wrote: > From: Martin Hundebøll <mhu@silicom.dk> > > The Max10 BMC on the Silicom n5010 PAC is slightly different than the > existing BMCs, so use a dedicated feature revision detect it. > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk> > Reviewed-by: Moritz Fischer <mdf@kernel.org> > --- > > Changes since v4: > * Moved spi board_info structure from global/static scope > to function/stack scope > > Changes since v3: > * Changed "BMC's" to "BMCs" > * Added Moritz' Reviewed-by > > Changes since v2: > * None > > Changes since v1: > * use feature revision from struct dfl_device instead of reading it > from io-mem > > drivers/spi/spi-altera-dfl.c | 21 ++++++++++++--------- > 1 file changed, 12 insertions(+), 9 deletions(-) > > diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c > index 39a3e1a032e0..44fc9ee13fc7 100644 > --- a/drivers/spi/spi-altera-dfl.c > +++ b/drivers/spi/spi-altera-dfl.c > @@ -104,13 +104,6 @@ static const struct regmap_config indirect_regbus_cfg = { > .reg_read = indirect_bus_reg_read, > }; > > -static struct spi_board_info m10_bmc_info = { > - .modalias = "m10-d5005", > - .max_speed_hz = 12500000, > - .bus_num = 0, > - .chip_select = 0, > -}; > - > static void config_spi_master(void __iomem *base, struct spi_master *master) > { > u64 v; > @@ -130,6 +123,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master) > > static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) > { > + struct spi_board_info board_info = { 0 }; > struct device *dev = &dfl_dev->dev; > struct spi_master *master; > struct altera_spi *hw; > @@ -170,9 +164,18 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) > goto exit; > } > > - if (!spi_new_device(master, &m10_bmc_info)) { > + if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010) > + strscpy(board_info.modalias, "m10-n5010", SPI_NAME_SIZE); > + else > + strscpy(board_info.modalias, "m10-d5005", SPI_NAME_SIZE); > + > + board_info.max_speed_hz = 12500000; > + board_info.bus_num = 0; > + board_info.chip_select = 0; > + > + if (!spi_new_device(master, &board_info)) { > dev_err(dev, "%s failed to create SPI device: %s\n", > - __func__, m10_bmc_info.modalias); > + __func__, board_info.modalias); > } > Looks good to me. Reviewed-by: Tom Rix <trix@redhat.com> > return 0; ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision 2021-07-16 20:44 ` Tom Rix @ 2021-07-29 20:05 ` Moritz Fischer 0 siblings, 0 replies; 11+ messages in thread From: Moritz Fischer @ 2021-07-29 20:05 UTC (permalink / raw) To: Tom Rix Cc: Martin Hundebøll, Wu Hao, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown, Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi On Fri, Jul 16, 2021 at 01:44:45PM -0700, Tom Rix wrote: > > On 7/16/21 6:54 AM, Martin Hundebøll wrote: > > From: Martin Hundebøll <mhu@silicom.dk> > > > > The Max10 BMC on the Silicom n5010 PAC is slightly different than the > > existing BMCs, so use a dedicated feature revision detect it. > > > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk> > > Reviewed-by: Moritz Fischer <mdf@kernel.org> > > --- > > > > Changes since v4: > > * Moved spi board_info structure from global/static scope > > to function/stack scope > > > > Changes since v3: > > * Changed "BMC's" to "BMCs" > > * Added Moritz' Reviewed-by > > > > Changes since v2: > > * None > > > > Changes since v1: > > * use feature revision from struct dfl_device instead of reading it > > from io-mem > > > > drivers/spi/spi-altera-dfl.c | 21 ++++++++++++--------- > > 1 file changed, 12 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c > > index 39a3e1a032e0..44fc9ee13fc7 100644 > > --- a/drivers/spi/spi-altera-dfl.c > > +++ b/drivers/spi/spi-altera-dfl.c > > @@ -104,13 +104,6 @@ static const struct regmap_config indirect_regbus_cfg = { > > .reg_read = indirect_bus_reg_read, > > }; > > -static struct spi_board_info m10_bmc_info = { > > - .modalias = "m10-d5005", > > - .max_speed_hz = 12500000, > > - .bus_num = 0, > > - .chip_select = 0, > > -}; > > - > > static void config_spi_master(void __iomem *base, struct spi_master *master) > > { > > u64 v; > > @@ -130,6 +123,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master) > > static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) > > { > > + struct spi_board_info board_info = { 0 }; > > struct device *dev = &dfl_dev->dev; > > struct spi_master *master; > > struct altera_spi *hw; > > @@ -170,9 +164,18 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) > > goto exit; > > } > > - if (!spi_new_device(master, &m10_bmc_info)) { > > + if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010) > > + strscpy(board_info.modalias, "m10-n5010", SPI_NAME_SIZE); > > + else > > + strscpy(board_info.modalias, "m10-d5005", SPI_NAME_SIZE); > > + > > + board_info.max_speed_hz = 12500000; > > + board_info.bus_num = 0; > > + board_info.chip_select = 0; > > + > > + if (!spi_new_device(master, &board_info)) { > > dev_err(dev, "%s failed to create SPI device: %s\n", > > - __func__, m10_bmc_info.modalias); > > + __func__, board_info.modalias); > > } > > Looks good to me. > > Reviewed-by: Tom Rix <trix@redhat.com> > > > return 0; > Applied to for-next, Thanks ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors 2021-07-16 13:54 [PATCH v5 0/3] fpga/spi/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll 2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll 2021-07-16 13:54 ` [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll @ 2021-07-16 13:54 ` Martin Hundebøll 2021-07-17 14:02 ` Guenter Roeck 2 siblings, 1 reply; 11+ messages in thread From: Martin Hundebøll @ 2021-07-16 13:54 UTC (permalink / raw) To: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Guenter Roeck, Mark Brown Cc: Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi From: Martin Hundebøll <mhu@silicom.dk> Add the list of sensors supported by the Silicom n5010 PAC, and enable the drivers as a subtype of the intel-m10-bmc multi-function driver. Signed-off-by: Martin Hundebøll <mhu@silicom.dk> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Moritz Fischer <mdf@kernel.org> Reviewed-by: Xu Yilun <yilun.xu@intel.com> --- Changes since v4: * None Changes since v3: * None Changes since v2: * Added Yilun's Reviewed-by * Added Moritz' Reviewed-by * Added Guenter's Reviewed-by Changes since v1: * Patch split out to separate hwmon changes drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c index bd7ed2ed3a1e..7a08e4c44a4b 100644 --- a/drivers/hwmon/intel-m10-bmc-hwmon.c +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = { .hinfo = d5005bmc_hinfo, }; +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = { + { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" }, + { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" }, + { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" }, + { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" }, + { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" }, + { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" }, + { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" }, + { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" }, + { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" }, + { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" }, + { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" }, + { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" }, + { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" }, + { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" }, + { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" }, + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" }, + { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" }, +}; + +static const struct m10bmc_sdata n5010bmc_in_tbl[] = { + { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" }, + { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" }, + { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" }, + { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" }, + { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" }, + { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" }, + { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" }, + { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" }, + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" }, + { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" }, + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" }, + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" }, + { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" }, +}; + +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = { + { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" }, + { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" }, + { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" }, + { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" }, + { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" }, + { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" }, + { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" }, + { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" }, + { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" }, + { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" }, + { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" }, + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" }, + { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" }, +}; + +static const struct hwmon_channel_info *n5010bmc_hinfo[] = { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL), + NULL +}; + +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = { + .tables = { + [hwmon_temp] = n5010bmc_temp_tbl, + [hwmon_in] = n5010bmc_in_tbl, + [hwmon_curr] = n5010bmc_curr_tbl, + }, + + .hinfo = n5010bmc_hinfo, +}; + static umode_t m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, int channel) @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = { .name = "d5005bmc-hwmon", .driver_data = (unsigned long)&d5005bmc_hwmon_bdata, }, + { + .name = "n5010bmc-hwmon", + .driver_data = (unsigned long)&n5010bmc_hwmon_bdata, + }, { } }; -- 2.31.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors 2021-07-16 13:54 ` [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll @ 2021-07-17 14:02 ` Guenter Roeck 0 siblings, 0 replies; 11+ messages in thread From: Guenter Roeck @ 2021-07-17 14:02 UTC (permalink / raw) To: Martin Hundebøll Cc: Wu Hao, Tom Rix, Moritz Fischer, Xu Yilun, Jean Delvare, Mark Brown, Martin Hundebøll, linux-fpga, linux-kernel, linux-hwmon, linux-spi On Fri, Jul 16, 2021 at 03:54:41PM +0200, Martin Hundebøll wrote: > From: Martin Hundebøll <mhu@silicom.dk> > > Add the list of sensors supported by the Silicom n5010 PAC, and enable > the drivers as a subtype of the intel-m10-bmc multi-function driver. > > Signed-off-by: Martin Hundebøll <mhu@silicom.dk> > Reviewed-by: Guenter Roeck <linux@roeck-us.net> > Reviewed-by: Moritz Fischer <mdf@kernel.org> > Reviewed-by: Xu Yilun <yilun.xu@intel.com> The context patches have been applied, so I applied this patch as well to hwmon-next. Guenter > --- > > Changes since v4: > * None > > Changes since v3: > * None > > Changes since v2: > * Added Yilun's Reviewed-by > * Added Moritz' Reviewed-by > * Added Guenter's Reviewed-by > > Changes since v1: > * Patch split out to separate hwmon changes > > drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c > index bd7ed2ed3a1e..7a08e4c44a4b 100644 > --- a/drivers/hwmon/intel-m10-bmc-hwmon.c > +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c > @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = { > .hinfo = d5005bmc_hinfo, > }; > > +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = { > + { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" }, > + { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" }, > + { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" }, > + { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" }, > + { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" }, > + { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" }, > + { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" }, > + { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" }, > + { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" }, > + { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" }, > + { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" }, > + { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" }, > + { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" }, > + { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" }, > + { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" }, > + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" }, > + { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" }, > +}; > + > +static const struct m10bmc_sdata n5010bmc_in_tbl[] = { > + { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" }, > + { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" }, > + { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" }, > + { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" }, > + { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" }, > + { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" }, > + { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" }, > + { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" }, > + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" }, > + { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" }, > + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" }, > + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" }, > + { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" }, > +}; > + > +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = { > + { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" }, > + { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" }, > + { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" }, > + { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" }, > + { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" }, > + { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" }, > + { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" }, > + { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" }, > + { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" }, > + { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" }, > + { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" }, > + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" }, > + { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" }, > +}; > + > +static const struct hwmon_channel_info *n5010bmc_hinfo[] = { > + HWMON_CHANNEL_INFO(temp, > + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL, > + HWMON_T_INPUT | HWMON_T_LABEL), > + HWMON_CHANNEL_INFO(in, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL, > + HWMON_I_INPUT | HWMON_I_LABEL), > + HWMON_CHANNEL_INFO(curr, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL, > + HWMON_C_INPUT | HWMON_C_LABEL), > + NULL > +}; > + > +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = { > + .tables = { > + [hwmon_temp] = n5010bmc_temp_tbl, > + [hwmon_in] = n5010bmc_in_tbl, > + [hwmon_curr] = n5010bmc_curr_tbl, > + }, > + > + .hinfo = n5010bmc_hinfo, > +}; > + > static umode_t > m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, > u32 attr, int channel) > @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = { > .name = "d5005bmc-hwmon", > .driver_data = (unsigned long)&d5005bmc_hwmon_bdata, > }, > + { > + .name = "n5010bmc-hwmon", > + .driver_data = (unsigned long)&n5010bmc_hwmon_bdata, > + }, > { } > }; > ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-07-29 20:05 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-16 13:54 [PATCH v5 0/3] fpga/spi/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll 2021-07-16 13:54 ` [PATCH v5 1/3] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll 2021-07-16 20:46 ` Tom Rix 2021-07-29 20:04 ` Moritz Fischer 2021-07-16 13:54 ` [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll 2021-07-16 17:33 ` Mark Brown 2021-07-17 23:56 ` Moritz Fischer 2021-07-16 20:44 ` Tom Rix 2021-07-29 20:05 ` Moritz Fischer 2021-07-16 13:54 ` [PATCH v5 3/3] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll 2021-07-17 14:02 ` Guenter Roeck
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