Hi Andy,

I love your patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v5.15 next-20211112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Andy-Shevchenko/fpga-dfl-pci-Use-pci_find_vsec_capability-when-looking-for-DFL/20211109-234228
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d2f38a3c6507b2520101f9a3807ed98f1bdc545a
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/dfc10076ac7a63331954a33cabf94a1af3632210
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Andy-Shevchenko/fpga-dfl-pci-Use-pci_find_vsec_capability-when-looking-for-DFL/20211109-234228
        git checkout dfc10076ac7a63331954a33cabf94a1af3632210
        # save the attached .config to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/fpga/dfl-pci.c: In function 'find_dfls_by_vsec':
>> drivers/fpga/dfl-pci.c:146:34: error: 'dev' undeclared (first use in this function); did you mean 'cdev'?
     146 |  voff = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_DFLS);
         |                                  ^~~
         |                                  cdev
   drivers/fpga/dfl-pci.c:146:34: note: each undeclared identifier is reported only once for each function it appears in


vim +146 drivers/fpga/dfl-pci.c

   138	
   139	static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info)
   140	{
   141		u32 bir, offset, dfl_cnt, dfl_res;
   142		resource_size_t start, len;
   143		int dfl_res_off, i, bars;
   144		u16 voff;
   145	
 > 146		voff = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_DFLS);
   147		if (!voff) {
   148			dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
   149			return -ENODEV;
   150		}
   151	
   152		dfl_cnt = 0;
   153		pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
   154		if (dfl_cnt > PCI_STD_NUM_BARS) {
   155			dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
   156				__func__, dfl_cnt, PCI_STD_NUM_BARS);
   157			return -EINVAL;
   158		}
   159	
   160		dfl_res_off = voff + PCI_VNDR_DFLS_RES;
   161		if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
   162			dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
   163				__func__);
   164			return -EINVAL;
   165		}
   166	
   167		for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
   168			dfl_res = GENMASK(31, 0);
   169			pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);
   170	
   171			bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
   172			if (bir >= PCI_STD_NUM_BARS) {
   173				dev_err(&pcidev->dev, "%s bad bir number %d\n",
   174					__func__, bir);
   175				return -EINVAL;
   176			}
   177	
   178			if (bars & BIT(bir)) {
   179				dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
   180					__func__, bir);
   181				return -EINVAL;
   182			}
   183	
   184			bars |= BIT(bir);
   185	
   186			len = pci_resource_len(pcidev, bir);
   187			offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
   188			if (offset >= len) {
   189				dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
   190					__func__, offset, &len);
   191				return -EINVAL;
   192			}
   193	
   194			dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);
   195	
   196			len -= offset;
   197	
   198			start = pci_resource_start(pcidev, bir) + offset;
   199	
   200			dfl_fpga_enum_info_add_dfl(info, start, len);
   201		}
   202	
   203		return 0;
   204	}
   205	

---
0-DAY CI Kernel Test Service, Intel Corporation
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