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From: Conor Dooley <conor.dooley@microchip.com>
To: <linux-fpga@vger.kernel.org>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	Moritz Fischer <mdf@kernel.org>, Wu Hao <hao.wu@intel.com>,
	Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, Rob Herring <robh@kernel.org>
Subject: [PATCH v2 2/7] dt-bindings: soc: microchip: add a property for system controller flash
Date: Fri, 31 Mar 2023 08:18:18 +0100	[thread overview]
Message-ID: <20230331071823.956087-3-conor.dooley@microchip.com> (raw)
In-Reply-To: <20230331071823.956087-1-conor.dooley@microchip.com>

The system controller "shares" a SPI flash device with a QSPI controller
in the MSS. This flash is used to store FPGA bitstreams & other
metadata. IAP and Auto Upgrade both write images to this flash that the
System Controller will use to re-program the FPGA.

Add a phandle property signifying which flash device is connected to the
system controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../soc/microchip/microchip,mpfs-sys-controller.yaml   | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 04ffee3a7c59..aee96c639af7 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -26,6 +26,16 @@ properties:
   compatible:
     const: microchip,mpfs-sys-controller
 
+  microchip,bitstream-flash:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      The SPI flash connected to the system controller's QSPI controller.
+      The system controller may retrieve FPGA bitstreams from this flash to
+      perform In-Application Programming (IAP) or during device initialisation
+      for Auto Update. The MSS and system controller have separate QSPI
+      controllers and this flash is connected to both. Software running in the
+      MSS can write bitstreams to the flash.
+
 required:
   - compatible
   - mboxes
-- 
2.39.2


  parent reply	other threads:[~2023-03-31  7:20 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-31  7:18 [PATCH v2 0/7] PolarFire SoC Auto Update Support Conor Dooley
2023-03-31  7:18 ` [PATCH v2 1/7] soc: microchip: mpfs: add a prefix to rx_callback() Conor Dooley
2023-03-31  7:18 ` Conor Dooley [this message]
2023-03-31  7:18 ` [PATCH v2 3/7] soc: microchip: mpfs: enable access to the system controller's flash Conor Dooley
2023-03-31  7:18 ` [PATCH v2 4/7] soc: microchip: mpfs: print service status in warning message Conor Dooley
2023-03-31  7:18 ` [PATCH v2 5/7] soc: microchip: mpfs: add auto-update subdev to system controller Conor Dooley
2023-03-31  7:18 ` [PATCH v2 6/7] fpga: add PolarFire SoC Auto Update support Conor Dooley
2023-04-02 10:57   ` Xu Yilun
2023-04-11 11:51     ` Conor Dooley
2023-04-14 12:40       ` Xu Yilun
2023-03-31  7:18 ` [PATCH v2 7/7] riscv: dts: microchip: add the mpfs' system controller qspi & associated flash Conor Dooley
2023-04-02  8:00 ` [PATCH v2 0/7] PolarFire SoC Auto Update Support Xu Yilun
2023-04-02  8:23   ` Conor Dooley
2023-04-03 19:34 ` (subset) " Conor Dooley

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