From: Russ Weight <russell.h.weight@intel.com>
To: Tom Rix <trix@redhat.com>, Xu Yilun <yilun.xu@intel.com>
Cc: <mdf@kernel.org>, <linux-fpga@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <lgoncalv@redhat.com>,
<hao.wu@intel.com>, <matthew.gerlach@intel.com>
Subject: Re: [PATCH v17 0/5] FPGA Image Load (previously Security Manager)
Date: Mon, 11 Oct 2021 18:00:16 -0700 [thread overview]
Message-ID: <336e4827-b09a-e1ab-b67d-d8755012d71c@intel.com> (raw)
In-Reply-To: <79350773-3629-2734-21c0-0314a762e722@redhat.com>
On 10/11/21 5:35 AM, Tom Rix wrote:
>
> On 10/10/21 6:41 PM, Xu Yilun wrote:
>> On Sat, Oct 09, 2021 at 05:11:20AM -0700, Tom Rix wrote:
>>> On 10/9/21 1:08 AM, Xu Yilun wrote:
>>>> On Wed, Sep 29, 2021 at 04:00:20PM -0700, Russ Weight wrote:
>>>>> The FPGA Image Load framework provides an API to upload image
>>>>> files to an FPGA device. Image files are self-describing. They could
>>>>> contain FPGA images, BMC images, Root Entry Hashes, or other device
>>>>> specific files. It is up to the lower-level device driver and the
>>>>> target device to authenticate and disposition the file data.
>>>> I've reconsider the FPGA persistent image update again, and think we
>>>> may include it in FPGA manager framework.
>>>>
>>>> Sorry I raised this topic again when it is already at patch v17, but now
>>>> I need to consider more seriously than before.
>>>>
>>>> We have consensus the FPGA persistent image update is just like a normal
>>>> firmware update which finally writes the nvmem like flash or eeprom,
>>>> while the current FPGA manager deals with the active FPGA region update
>>>> and re-activation. Could we just expand the FPGA manager and let it handle
>>>> the nvmem update as well? Many FPGA cards have nvmem and downloaders
>>>> supports updating both FPGA region and nvmem.
The fpga-image-load driver is actually just a data transfer. The class
driver has no knowledge about what the data is or where/if the data will
be stored.
This functionality could, of course, be merged into the fpga-mgr. I did
a proof of concept of this a while back and we discussed the pros and cons.
See this email for a recap:
https://marc.info/?l=linux-fpga&m=161998085507374&w=2
Things have changed some with the evolution of the driver. The IOCTL
approach probably fits better than the sysfs implementation. At the time
it seemed that a merge would add unnecessary complexity without adding value.
>>>>
>>>> According to the patchset, the basic workflow of the 2 update types are
>>>> quite similar, get the data, prepare for the HW, write and complete.
>>>> They are already implemented in FPGA manager. We've discussed some
>>>> differences like threading or canceling the update, which are
>>>> not provided by FPGA manager but they may also nice to have for FPGA
>>>> region update. An FPGA region update may also last for a long time??
>>>> So I think having 2 sets of similar frameworks in FPGA is unnecessary.
>>>>
>>>> My quick mind is that we add some flags in struct fpga_mgr & struct
>>>> fpga_image_info to indicate the HW capability (support FPGA region
>>>> update or nvmem update or both) of the download engine and the provided
>>>> image type. Then the low-level driver knows how to download if it
>>>> supports both image types.An char device could be added for each fpga manager dev, providing the
>>>> user APIs for nvmem update. We may not use the char dev for FPGA region
>>>> update cause it changes the system HW devices and needs device hotplug
>>>> in FPGA region. We'd better leave it to FPGA region class, this is
>>>> another topic.
I'll give this some more thought and see if I can come up with some RFC
patches.
- Russ
>>>>
>>>> More discussion is appreciated.
>>> I also think fpga_mgr could be extended.
>>>
>>> In this patchset,
>>>
>>> https://lore.kernel.org/linux-fpga/20210625195849.837976-1-trix@redhat.com/
>>>
>>> A second, similar set of write ops was added to fpga_manger_ops,
>>>
>>> new bit/flag was added to fpga_image_info
>>>
>>> The intent was for dfl to add their specific ops to cover what is done in
>>> this patchset.
>> I think we don't have to add 2 ops for reconfig & reimage in framework,
>> the 2 processes are almost the same.
>>
>> Just add the _REIMAGE (or something else, NVMEM?) flag for
>> fpga_image_info, and low level drivers handle it as they do for other
>> flags.
>>
>> How do you think?
>
> A single set is fine.
>
> A difficult part of is the length of time to do the write. The existing write should be improved to use a worker thread.
>
> Tom
>
>>
>> Thanks,
>> Yilun
>>
>>> Any other driver would do similar.
>>>
>>> Is this close to what you are thinking ?
>>>
>>> Tom
>>>
>>>> Thanks,
>>>> Yilun
>>>>
>
next prev parent reply other threads:[~2021-10-12 1:00 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-29 23:00 [PATCH v17 0/5] FPGA Image Load (previously Security Manager) Russ Weight
2021-09-29 23:00 ` [PATCH v17 1/5] fpga: image-load: fpga image load framework Russ Weight
2021-09-29 23:00 ` [PATCH v17 2/5] fpga: image-load: enable image uploads Russ Weight
2021-10-06 18:13 ` Russ Weight
2021-09-29 23:00 ` [PATCH v17 3/5] fpga: image-load: signal eventfd when complete Russ Weight
2021-09-29 23:00 ` [PATCH v17 4/5] fpga: image-load: add status ioctl Russ Weight
2021-10-15 20:22 ` Lizhi Hou
2021-10-20 21:42 ` Russ Weight
2021-10-26 0:07 ` Lizhi Hou
2021-09-29 23:00 ` [PATCH v17 5/5] fpga: image-load: enable cancel of image upload Russ Weight
2021-10-09 8:08 ` [PATCH v17 0/5] FPGA Image Load (previously Security Manager) Xu Yilun
2021-10-09 12:11 ` Tom Rix
2021-10-11 1:41 ` Xu Yilun
2021-10-11 12:35 ` Tom Rix
2021-10-12 1:00 ` Russ Weight [this message]
2021-10-12 7:47 ` Xu Yilun
2021-10-12 7:56 ` Xu Yilun
2021-10-12 17:20 ` Russ Weight
2021-10-13 1:06 ` Xu Yilun
2021-10-13 18:09 ` Russ Weight
2021-10-14 1:49 ` Xu Yilun
[not found] ` <7d1971d0-b50b-077f-2a82-83d822cd2ad7@intel.com>
2021-10-15 2:51 ` Xu Yilun
2021-10-15 17:34 ` Russ Weight
2021-10-18 8:13 ` Xu Yilun
2021-10-18 16:24 ` Russ Weight
2021-10-19 2:53 ` Xu Yilun
2021-10-19 15:09 ` Russ Weight
2021-10-20 1:16 ` Xu Yilun
2021-10-20 16:27 ` Russ Weight
2021-10-26 6:45 ` Wu, Hao
2021-10-26 17:41 ` Russ Weight
2021-10-27 3:29 ` Wu, Hao
2021-10-27 15:11 ` Russ Weight
2021-10-27 15:34 ` Tom Rix
2021-10-28 15:09 ` Xu Yilun
2021-10-28 16:08 ` Tom Rix
2021-10-29 2:05 ` Xu Yilun
2021-10-12 7:49 ` Xu Yilun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=336e4827-b09a-e1ab-b67d-d8755012d71c@intel.com \
--to=russell.h.weight@intel.com \
--cc=hao.wu@intel.com \
--cc=lgoncalv@redhat.com \
--cc=linux-fpga@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=matthew.gerlach@intel.com \
--cc=mdf@kernel.org \
--cc=trix@redhat.com \
--cc=yilun.xu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).