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Mon, 1 Feb 2021 07:15:29 -0800 Envelope-to: dragos.bogdan@analog.com, ardeleanalex@gmail.com, mdf@kernel.org, linux-fpga@vger.kernel.org, lars@metafoo.de, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, alexandru.ardelean@analog.com Received: from [172.30.17.109] (port=37420) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1l6avJ-000343-Kl; Mon, 01 Feb 2021 07:15:29 -0800 Subject: Re: [PATCH v3 1/4] clk: axi-clkgen: replace ARCH dependencies with driver deps To: Alexandru Ardelean , , , CC: , , , , , , , Dragos Bogdan References: <20210201151245.21845-1-alexandru.ardelean@analog.com> <20210201151245.21845-2-alexandru.ardelean@analog.com> From: Michal Simek Message-ID: <3be0501f-98bf-8371-6994-e77c94b4597b@xilinx.com> Date: Mon, 1 Feb 2021 16:15:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <20210201151245.21845-2-alexandru.ardelean@analog.com> Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2021 15:15:30.3582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82e75972-71a6-47ba-738f-08d8c6c43692 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT027.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5880 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org On 2/1/21 4:12 PM, Alexandru Ardelean wrote: > The intent is to be able to run this driver to access the IP core in setups > where FPGA board is also connected via a PCIe bus. In such cases the number > of combinations explodes, where the host system can be an x86 with Xilinx > Zynq/ZynqMP/Microblaze board connected via PCIe. > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. > > To accommodate for these cases, this change removes the limitation for this > driver to be compilable only on Zynq/Microblaze architectures. > And adds dependencies on the mechanisms required by the driver to work (OF > and HAS_IOMEM). > > Signed-off-by: Dragos Bogdan > Signed-off-by: Alexandru Ardelean > --- > drivers/clk/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 85856cff506c..cee1d4e657bc 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -247,7 +247,8 @@ config CLK_TWL6040 > > config COMMON_CLK_AXI_CLKGEN > tristate "AXI clkgen driver" > - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST > + depends on HAS_IOMEM || COMPILE_TEST > + depends on OF > help > Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx > FPGAs. It is commonly used in Analog Devices' reference designs. > Make sense. Acked-by: Michal Simek Thanks, Michal