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Mon, 12 Jul 2021 01:27:51 +0000 From: "Wu, Hao" To: "trix@redhat.com" , "mdf@kernel.org" , "corbet@lwn.net" CC: "linux-fpga@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v2 3/4] fpga: dfl: implement the compat_id_show region op Thread-Topic: [PATCH v2 3/4] fpga: dfl: implement the compat_id_show region op Thread-Index: AQHXdMhaYtV05DKfXECOPKHkfysLZKs+jdGA Date: Mon, 12 Jul 2021 01:27:51 +0000 Message-ID: References: <20210709134229.2510349-1-trix@redhat.com> <20210709134229.2510349-5-trix@redhat.com> In-Reply-To: <20210709134229.2510349-5-trix@redhat.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d83986f0-9008-41a9-1a18-08d944d4441f x-ms-traffictypediagnostic: DM6PR11MB4594: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3819.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d83986f0-9008-41a9-1a18-08d944d4441f X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jul 2021 01:27:51.5820 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XaNiJKDKA7kVExKRr32zY8c/+ZMJxANlbKhcknR2XS0+SivO9Pipl+T3IpQpTV9Eit2+LevuRLfdA4BYYibeXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4594 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org > Subject: [PATCH v2 3/4] fpga: dfl: implement the compat_id_show region op >=20 > From: Tom Rix >=20 > Make sure dfl will work as previously when compat_id is removed > from struct fpga_manager. Store and pass the compat_id values > internal to dfl. >=20 > Signed-off-by: Tom Rix > --- > drivers/fpga/dfl-fme-mgr.c | 16 +++++++++++++--- > drivers/fpga/dfl-fme-region.c | 14 ++++++++++++++ > drivers/fpga/dfl.h | 14 ++++++++++++++ > 3 files changed, 41 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c > index d5861d13b3069..cd0b9157ea6e5 100644 > --- a/drivers/fpga/dfl-fme-mgr.c > +++ b/drivers/fpga/dfl-fme-mgr.c > @@ -22,6 +22,7 @@ > #include > #include >=20 > +#include "dfl.h" > #include "dfl-fme-pr.h" >=20 > /* FME Partial Reconfiguration Sub Feature Register Set */ > @@ -70,6 +71,7 @@ > struct fme_mgr_priv { > void __iomem *ioaddr; > u64 pr_error; > + struct dfl_compat_id compat_id; > }; >=20 > static u64 pr_error_to_mgr_status(u64 err) > @@ -272,13 +274,21 @@ static const struct fpga_manager_ops fme_mgr_ops > =3D { > .status =3D fme_mgr_status, > }; >=20 > -static void fme_mgr_get_compat_id(void __iomem *fme_pr, > - struct fpga_compat_id *id) > +static void _fme_mgr_get_compat_id(void __iomem *fme_pr, > + struct dfl_compat_id *id) > { > id->id_l =3D readq(fme_pr + FME_PR_INTFC_ID_L); > id->id_h =3D readq(fme_pr + FME_PR_INTFC_ID_H); > } >=20 > +void fme_mgr_get_compat_id(struct fpga_manager *mgr, > + struct dfl_compat_id *id) > +{ > + struct fme_mgr_priv *priv =3D mgr->priv; > + *id =3D priv->compat_id; > +} > +EXPORT_SYMBOL_GPL(fme_mgr_get_compat_id); > + > static int fme_mgr_probe(struct platform_device *pdev) > { > struct dfl_fme_mgr_pdata *pdata =3D dev_get_platdata(&pdev->dev); > @@ -306,7 +316,7 @@ static int fme_mgr_probe(struct platform_device *pdev= ) > if (!compat_id) > return -ENOMEM; >=20 > - fme_mgr_get_compat_id(priv->ioaddr, compat_id); > + _fme_mgr_get_compat_id(priv->ioaddr, &priv->compat_id); >=20 > mgr =3D devm_fpga_mgr_create(dev, "DFL FME FPGA Manager", > &fme_mgr_ops, priv); > diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl-fme-region.= c > index ca7277d3d30a9..d21eacbf2469f 100644 > --- a/drivers/fpga/dfl-fme-region.c > +++ b/drivers/fpga/dfl-fme-region.c > @@ -17,6 +17,7 @@ > #include > #include >=20 > +#include "dfl.h" > #include "dfl-fme-pr.h" >=20 > static int fme_region_get_bridges(struct fpga_region *region) > @@ -27,8 +28,21 @@ static int fme_region_get_bridges(struct fpga_region > *region) > return fpga_bridge_get_to_list(dev, region->info, ®ion->bridge_list)= ; > } >=20 > +static ssize_t fme_region_compat_id_show(struct fpga_region *region, cha= r > *buf) > +{ > + struct fpga_manager *mgr =3D region->mgr; > + struct dfl_compat_id compat_id; > + > + fme_mgr_get_compat_id(mgr, &compat_id); It's better to have a common interface, otherwise this region driver depend= s on one specific mgr driver FPGA_DFL_FME_MGR. Ideally this region driver can be reused with a new fpga mgr driver. Compat id can be per-region or shared one from fpga-mgr. In this hardware, = all regions share the same compat_id from fpga-mgr. I think reuse fpga-mgr compatibility id can be done via fpga-mgr data struc= ture or some common API exposed by fpga-mgr. In the first implementation, we added it to fpga-mgr data structure which has less code. Thanks Hao > + > + return sysfs_emit(buf, "%016llx%016llx\n", > + (unsigned long long)compat_id.id_h, > + (unsigned long long)compat_id.id_l); > +} > + > static const struct fpga_region_ops fme_fpga_region_ops =3D { > .get_bridges =3D fme_region_get_bridges, > + .compat_id_show =3D fme_region_compat_id_show, > }; >=20 > static int fme_region_probe(struct platform_device *pdev) > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > index 2b82c96ba56c7..a83fd11b390fc 100644 > --- a/drivers/fpga/dfl.h > +++ b/drivers/fpga/dfl.h > @@ -169,6 +169,20 @@ > #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts > num */ > #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector > */ >=20 > +/** > + * struct dfl_compat_id - id for compatibility check > + * > + * @id_h: high 64bit of the compat_id > + * @id_l: low 64bit of the compat_id > + */ > +struct dfl_compat_id { > + u64 id_h; > + u64 id_l; > +}; > + > +void fme_mgr_get_compat_id(struct fpga_manager *mgr, > + struct dfl_compat_id *id); > + > /** > * struct dfl_fpga_port_ops - port ops > * > -- > 2.26.3