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From: Moritz Fischer <mdf@kernel.org>
To: Nava kishore Manne <nava.manne@xilinx.com>
Cc: mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org,
	michal.simek@xilinx.com, linux-fpga@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, git@xilinx.com
Subject: Re: [PATCH 2/3] fpga: region: Add fpga-region property 'power-domains'
Date: Fri, 2 Apr 2021 10:15:38 -0700	[thread overview]
Message-ID: <YGdROrOOzltI/Bbe@epycbox.lan> (raw)
In-Reply-To: <20210402092049.479-3-nava.manne@xilinx.com>

On Fri, Apr 02, 2021 at 02:50:48PM +0530, Nava kishore Manne wrote:
> Add fpga-region property 'power-domains' to allow to handle
> the FPGA/PL power domins.
> 
> dt-bindings: fpga: Enable PM generic domain support
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
>  .../devicetree/bindings/fpga/fpga-region.txt       | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt
> index e811cf825019..969ca53bb65e 100644
> --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt
> +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt
> @@ -196,6 +196,20 @@ Optional properties:
>  - config-complete-timeout-us : The maximum time in microseconds time for the
>  	FPGA to go to operating mode after the region has been programmed.
>  - child nodes : devices in the FPGA after programming.
> +- power-domains : A phandle and PM domain specifier as defined by bindings of
> +	the power controller specified by phandle.
> +Example:
> +	fpga_full: fpga-full {
> +                compatible = "fpga-region";
> +                fpga-mgr = <&zynqmp_pcap>;
> +                #address-cells = <2>;
> +                #size-cells = <2>;
> +                ranges;
> +                power-domains = <&zynqmp_firmware PL_PD>;
> +        };
> +
> +	The PL_PD power domain will be turned on before loading the bitstream
> +and turned off while removing/unloading the bitstream using overlays.

Can multiple regions share a power-domain or is this specific to full
fpga reconfiguration?

- Moritz

  reply	other threads:[~2021-04-02 17:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02  9:20 [PATCH 0/3]Enable PM generic domain support Nava kishore Manne
2021-04-02  9:20 ` [PATCH 1/3] dt-bindings: zynqmp: Add new PD_PL macro Nava kishore Manne
2021-04-09 14:47   ` Rob Herring
2021-04-02  9:20 ` [PATCH 2/3] fpga: region: Add fpga-region property 'power-domains' Nava kishore Manne
2021-04-02 17:15   ` Moritz Fischer [this message]
2021-04-05  8:46     ` Nava kishore Manne
2021-04-09 14:50   ` Rob Herring
2021-04-02  9:20 ` [PATCH 3/3] fpga: region: Adds runtime PM support Nava kishore Manne
2021-04-09 21:30   ` Moritz Fischer
2021-04-19  5:18     ` Nava kishore Manne
2021-06-02 10:48       ` Nava kishore Manne
2021-06-02 20:39         ` Tom Rix
2021-06-02 13:02   ` Johan Hovold

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