From: Luca Ceresoli <luca@lucaceresoli.net>
To: Tom Rix <trix@redhat.com>, linux-fpga@vger.kernel.org
Cc: Moritz Fischer <mdf@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Anatolij Gustschin <agust@denx.de>
Subject: Re: [PATCH v2 3/5] fpga manager: xilinx-spi: rework write_complete loop implementation
Date: Thu, 27 Aug 2020 21:26:02 +0200 [thread overview]
Message-ID: <bc35f12e-6ff2-94a7-d519-94616f6dfc6c@lucaceresoli.net> (raw)
In-Reply-To: <2b8d9ed7-0468-9001-2f8e-386312aae6cb@redhat.com>
Hi Tom,
thanks for the prompt feedback!
On 27/08/20 20:59, Tom Rix wrote:
>
> On 8/27/20 7:32 AM, Luca Ceresoli wrote:
>> In preparation to add error checking for gpiod_get_value(), rework
>> the loop to avoid the duplication of these lines:
>>
>> if (gpiod_get_value(conf->done))
>> return xilinx_spi_apply_cclk_cycles(conf);
>>
>> There is little advantage in this rework with current code. However
>> error checking will expand these two lines to five, making code
>> duplication more annoying.
>>
>> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
>>
>> ---
>>
>> This patch is new in v2
>> ---
>> drivers/fpga/xilinx-spi.c | 15 ++++++---------
>> 1 file changed, 6 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
>> index 01f494172379..cfc933d70f52 100644
>> --- a/drivers/fpga/xilinx-spi.c
>> +++ b/drivers/fpga/xilinx-spi.c
>> @@ -151,22 +151,19 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr,
>> struct fpga_image_info *info)
>> {
>> struct xilinx_spi_conf *conf = mgr->priv;
>> - unsigned long timeout;
>> + unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
>> int ret;
>>
>> - if (gpiod_get_value(conf->done))
>> - return xilinx_spi_apply_cclk_cycles(conf);
>> -
>> - timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
>> + while (true) {
>> + if (gpiod_get_value(conf->done))
>> + return xilinx_spi_apply_cclk_cycles(conf);
>>
>> - while (time_before(jiffies, timeout)) {
>> + if (time_after(jiffies, timeout))
>> + break;
>>
>> ret = xilinx_spi_apply_cclk_cycles(conf);
>> if (ret)
>> return ret;
>> -
>> - if (gpiod_get_value(conf->done))
>> - return xilinx_spi_apply_cclk_cycles(conf);
>> }
>
> Do you need another
>
> if (gpiod_get_value(conf->done))
> return xilinx_spi_apply_cclk_cycles(conf);
>
> here to cover the chance of sleeping in the loop ?
If I got your question correctly: if we get here it's because of a
timeout, thus programming has failed (DONE didn't come up after some
time), and checking it one more here seems pointless.
Does this reply your question?
--
Luca
next prev parent reply other threads:[~2020-08-27 19:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-27 14:32 [PATCH v2 1/5] fpga manager: xilinx-spi: remove stray comment Luca Ceresoli
2020-08-27 14:32 ` [PATCH v2 2/5] fpga manager: xilinx-spi: remove final dot from dev_err() strings Luca Ceresoli
2020-08-27 14:32 ` [PATCH v2 3/5] fpga manager: xilinx-spi: rework write_complete loop implementation Luca Ceresoli
2020-08-27 18:59 ` Tom Rix
2020-08-27 19:26 ` Luca Ceresoli [this message]
[not found] ` <27bbb896-fedf-6a3a-7220-5c57239a3b87@redhat.com>
2020-08-28 6:38 ` Luca Ceresoli
2020-08-28 12:34 ` Tom Rix
2020-08-27 14:32 ` [PATCH v2 4/5] fpga manager: xilinx-spi: add error checking after gpiod_get_value() Luca Ceresoli
2020-08-27 19:04 ` Tom Rix
2020-08-27 14:32 ` [PATCH v2 5/5] fpga manager: xilinx-spi: provide better diagnostics on programming failure Luca Ceresoli
2020-08-27 19:09 ` Tom Rix
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