From: Eric Biggers <ebiggers@kernel.org>
To: linux-mmc@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-fscrypt@vger.kernel.org,
Satya Tangirala <satyat@google.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Asutosh Das <asutoshd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Neeraj Soni <neersoni@codeaurora.org>,
Barani Muthukumaran <bmuthuku@codeaurora.org>,
Peng Zhou <peng.zhou@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH v6 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock
Date: Mon, 25 Jan 2021 10:38:08 -0800 [thread overview]
Message-ID: <20210125183810.198008-8-ebiggers@kernel.org> (raw)
In-Reply-To: <20210125183810.198008-1-ebiggers@kernel.org>
From: Eric Biggers <ebiggers@google.com>
Document the bindings for the registers and clock for the MMC instance
of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings
are needed in order for sdhci-msm to support inline encryption.
Reviewed-by: Satya Tangirala <satyat@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 9fa8a24fbc97d..4c7fa6a4ed15c 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -31,10 +31,12 @@ Required properties:
- SD Core register map (required for controllers earlier than msm-v5)
- CQE register map (Optional, CQE support is present on SDHC instance meant
for eMMC and version v4.2 and above)
+ - Inline Crypto Engine register map (optional)
- reg-names: When CQE register map is supplied, below reg-names are required
- "hc" for Host controller register map
- "core" for SD core register map
- "cqhci" for CQE register map
+ - "ice" for Inline Crypto Engine register map (optional)
- interrupts: Should contain an interrupt-specifiers for the interrupts:
- Host controller interrupt (required)
- pinctrl-names: Should contain only one value - "default".
@@ -47,6 +49,7 @@ Required properties:
"xo" - TCXO clock (optional)
"cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional)
+ "ice" - clock for Inline Crypto Engine (optional)
- qcom,ddr-config: Certain chipsets and platforms require particular settings
for the DDR_CONFIG register. Use this field to specify the register
--
2.30.0
next prev parent reply other threads:[~2021-01-26 19:13 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 18:38 [PATCH v6 0/9] eMMC inline encryption support Eric Biggers
2021-01-25 18:38 ` [PATCH v6 1/9] mmc: add basic support for inline encryption Eric Biggers
2021-01-25 18:38 ` [PATCH v6 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2021-01-25 18:38 ` [PATCH v6 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2021-01-25 21:24 ` Eric Biggers
2021-01-25 18:38 ` [PATCH v6 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2021-01-25 18:38 ` [PATCH v6 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2021-01-25 18:38 ` [PATCH v6 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2021-01-25 18:38 ` Eric Biggers [this message]
2021-01-25 18:38 ` [PATCH v6 8/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers
2021-01-25 18:38 ` [PATCH v6 9/9] arm64: dts: qcom: sdm630: add ICE registers and clocks Eric Biggers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210125183810.198008-8-ebiggers@kernel.org \
--to=ebiggers@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=agross@kernel.org \
--cc=asutoshd@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=bmuthuku@codeaurora.org \
--cc=devicetree@vger.kernel.org \
--cc=konradybcio@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-fscrypt@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=neersoni@codeaurora.org \
--cc=peng.zhou@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=satyat@google.com \
--cc=stanley.chu@mediatek.com \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).