From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E01C43333 for ; Tue, 26 Jan 2021 05:55:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 379332223D for ; Tue, 26 Jan 2021 05:55:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388840AbhAZFzr (ORCPT ); Tue, 26 Jan 2021 00:55:47 -0500 Received: from mail.kernel.org ([198.145.29.99]:44844 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732335AbhAZDPL (ORCPT ); Mon, 25 Jan 2021 22:15:11 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 121BD22B3F; Tue, 26 Jan 2021 00:15:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611620116; bh=cX3hhlW1d9/YsB6hj6Qe4lavdDpm38z9XYx4ck60cDE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TOhwCDaBYtIiDMkwl5c8+FMG7ZL+sc6YXZYcQK1oZKLaDHGEFAk7V6Jx13+UdN3HW dgliD1jTkIonfLbPwgTZPL0+TIlfcVrPF7DuMBys2SPvgzXQUG+pU8PBKa2FLZNB96 E7sOpZuOscjJWLWLirk9PoTDdLi9Py9NHy+Jk3iFMEkbZgdtoPiO2illCCvKXC5bbK I9MI490tcr0SnzSVoT8Mxl7+3Pv3J9KKdl+LB2OD6EAXor75C/e4XGF2uO/F+VHLdG qQJl2T0mZfRzkXJMbOZ/oeZbd6R4KXHJEqB5IMCqoTjH0PoOSiqOWSCnnS5dTI4m6v isCHYmoGuRRgA== From: Eric Biggers To: linux-mmc@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-fscrypt@vger.kernel.org, Satya Tangirala , Ulf Hansson , Andy Gross , Bjorn Andersson , Adrian Hunter , Asutosh Das , Rob Herring , Neeraj Soni , Barani Muthukumaran , Peng Zhou , Stanley Chu , Konrad Dybcio , Rob Herring Subject: [PATCH RESEND v6 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Date: Mon, 25 Jan 2021 16:14:54 -0800 Message-Id: <20210126001456.382989-8-ebiggers@kernel.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210126001456.382989-1-ebiggers@kernel.org> References: <20210126001456.382989-1-ebiggers@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-fscrypt@vger.kernel.org From: Eric Biggers Document the bindings for the registers and clock for the MMC instance of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings are needed in order for sdhci-msm to support inline encryption. Reviewed-by: Satya Tangirala Acked-by: Rob Herring Signed-off-by: Eric Biggers --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 9fa8a24fbc97d..4c7fa6a4ed15c 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -31,10 +31,12 @@ Required properties: - SD Core register map (required for controllers earlier than msm-v5) - CQE register map (Optional, CQE support is present on SDHC instance meant for eMMC and version v4.2 and above) + - Inline Crypto Engine register map (optional) - reg-names: When CQE register map is supplied, below reg-names are required - "hc" for Host controller register map - "core" for SD core register map - "cqhci" for CQE register map + - "ice" for Inline Crypto Engine register map (optional) - interrupts: Should contain an interrupt-specifiers for the interrupts: - Host controller interrupt (required) - pinctrl-names: Should contain only one value - "default". @@ -47,6 +49,7 @@ Required properties: "xo" - TCXO clock (optional) "cal" - reference clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional) + "ice" - clock for Inline Crypto Engine (optional) - qcom,ddr-config: Certain chipsets and platforms require particular settings for the DDR_CONFIG register. Use this field to specify the register -- 2.30.0