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[35.233.137.154]) by smtp.gmail.com with ESMTPSA id w4sm296254pjc.52.2020.12.08.15.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 15:54:28 -0800 (PST) Date: Tue, 8 Dec 2020 23:54:24 +0000 From: Satya Tangirala To: Eric Biggers Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-fscrypt@vger.kernel.org, Ulf Hansson , Andy Gross , Bjorn Andersson , Adrian Hunter , Asutosh Das , Rob Herring , Neeraj Soni , Barani Muthukumaran , Peng Zhou , Stanley Chu , Konrad Dybcio Subject: Re: [PATCH v2 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Message-ID: References: <20201203020516.225701-1-ebiggers@kernel.org> <20201203020516.225701-8-ebiggers@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201203020516.225701-8-ebiggers@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-fscrypt@vger.kernel.org On Wed, Dec 02, 2020 at 06:05:14PM -0800, Eric Biggers wrote: > From: Eric Biggers > > Document the bindings for the registers and clock for the MMC instance > of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings > are needed in order for sdhci-msm to support inline encryption. > > Signed-off-by: Eric Biggers > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > index 3b602fd6180bf..4f2e138439506 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt > @@ -30,10 +30,12 @@ Required properties: > - SD Core register map (required for controllers earlier than msm-v5) > - CQE register map (Optional, CQE support is present on SDHC instance meant > for eMMC and version v4.2 and above) > + - Inline Crypto Engine register map (optional) > - reg-names: When CQE register map is supplied, below reg-names are required > - "hc" for Host controller register map > - "core" for SD core register map > - "cqhci" for CQE register map > + - "ice" for Inline Crypto Engine register map (optional) > - interrupts: Should contain an interrupt-specifiers for the interrupts: > - Host controller interrupt (required) > - pinctrl-names: Should contain only one value - "default". > @@ -46,6 +48,7 @@ Required properties: > "xo" - TCXO clock (optional) > "cal" - reference clock for RCLK delay calibration (optional) > "sleep" - sleep clock for RCLK delay calibration (optional) > + "ice" - clock for Inline Crypto Engine (optional) > > - qcom,ddr-config: Certain chipsets and platforms require particular settings > for the DDR_CONFIG register. Use this field to specify the register > -- > 2.29.2 > Looks good to me. Please feel free to add Reviewed-by: Satya Tangirala