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From: James Bottomley <James.Bottomley@HansenPartnership.com>
To: Al Viro <viro@zeniv.linux.org.uk>
Cc: paulmck@linux.ibm.com, Eric Biggers <ebiggers@kernel.org>,
	"Tobin C. Harding" <me@tobin.cc>,
	linux-fsdevel@vger.kernel.org
Subject: Re: dcache locking question
Date: Sat, 16 Mar 2019 21:23:16 -0700	[thread overview]
Message-ID: <1552796596.6551.17.camel@HansenPartnership.com> (raw)
In-Reply-To: <20190317030634.GG2217@ZenIV.linux.org.uk>

On Sun, 2019-03-17 at 03:06 +0000, Al Viro wrote:
> On Sat, Mar 16, 2019 at 07:20:20PM -0700, James Bottomley wrote:
> > On Sat, 2019-03-16 at 17:50 -0700, Paul E. McKenney wrote:
> > [...]
> > >  I -have- seen stores of constant values be torn, but not stores
> > > of runtime-variable values and not loads.  Still, such tearing is
> > > permitted, and including the READ_ONCE() is making it easier for
> > > things like thread sanitizers.  In addition, the READ_ONCE()
> > > makes it clear that the value being loaded is unstable, which can
> > > be useful documentation.
> > 
> > Um, just so I'm clear, because this assumption permeates all our
> > code: load or store tearing can never occur if we're doing load or
> > store of a 32 bit value which is naturally aligned.  Where
> > naturally aligned is within the gift of the CPU to determine but
> > which the compiler or kernel will always ensure for us unless we
> > pack the structure or deliberately misalign the allocation.
> 
> Wait a sec; are there any 64bit architectures where the same is not
> guaranteed for dereferencing properly aligned void **?

Yes, naturally alligned void * dereference shouldn't tear either.  I
was just using 32 bit as my example because 64 bit accesses will tear
on 32 bit architectures but 64 bit naturally aligned accesses shouldn't
tear on 64 bit architectures.  However, since we can't guarantee the 64
bitness of the architecture 32 bit or void * is our gold standard for
not tearing.

James


> If that's the case, I can think of quite a few places that are rather
> dubious, and I don't see how READ_ONCE() could help in those - e.g.
> if an architecture only has 32bit loads, rcu list traversals are
> not going to be doable without one hell of an extra headache.
> 


  reply	other threads:[~2019-03-17  4:23 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-14 22:56 dcache locking question Tobin C. Harding
2019-03-14 23:09 ` Matthew Wilcox
2019-03-15  1:38   ` Tobin C. Harding
2019-03-14 23:19 ` Tobin C. Harding
2019-03-15  1:50   ` Al Viro
2019-03-15 17:38     ` Eric Biggers
2019-03-15 18:54       ` Al Viro
2019-03-16 22:31         ` Paul E. McKenney
2019-03-17  0:18           ` Al Viro
2019-03-17  0:50             ` Paul E. McKenney
2019-03-17  2:20               ` James Bottomley
2019-03-17  3:06                 ` Al Viro
2019-03-17  4:23                   ` James Bottomley [this message]
2019-03-18  0:35                     ` Paul E. McKenney
2019-03-18 16:26                       ` James Bottomley
2019-03-18 17:11                         ` Paul E. McKenney
2019-03-19 15:45                           ` Paul E. McKenney

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