From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48777C43457 for ; Tue, 13 Oct 2020 18:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14E60214D8 for ; Tue, 13 Oct 2020 18:31:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729755AbgJMSbx (ORCPT ); Tue, 13 Oct 2020 14:31:53 -0400 Received: from mga18.intel.com ([134.134.136.126]:39019 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726899AbgJMSbx (ORCPT ); Tue, 13 Oct 2020 14:31:53 -0400 IronPort-SDR: W8xiilTl3OxH88FCikgy1IOVIU6wcB8PvfhYPPZmjweOK2+8giAVSEDMuyYi9VfZKLhhtV00Li LJlK0kbY9ycg== X-IronPort-AV: E=McAfee;i="6000,8403,9773"; a="153794227" X-IronPort-AV: E=Sophos;i="5.77,371,1596524400"; d="scan'208";a="153794227" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 11:31:45 -0700 IronPort-SDR: N1xn0HQI0ubXW+ZZ5gn2QreU7BQoHP/0atyUS215Vn7NRjG/ItSebl73LdP+GjPjSK62O2AOZS e/mlDqFbQs2A== X-IronPort-AV: E=Sophos;i="5.77,371,1596524400"; d="scan'208";a="346279150" Received: from murawskx-mobl.amr.corp.intel.com (HELO [10.209.9.29]) ([10.209.9.29]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 11:31:45 -0700 Subject: Re: [PATCH RFC V3 4/9] x86/pks: Preserve the PKRS MSR on context switch To: ira.weiny@intel.com, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Peter Zijlstra Cc: Fenghua Yu , x86@kernel.org, Dave Hansen , Dan Williams , Andrew Morton , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org References: <20201009194258.3207172-1-ira.weiny@intel.com> <20201009194258.3207172-5-ira.weiny@intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201009194258.3207172-5-ira.weiny@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org On 10/9/20 12:42 PM, ira.weiny@intel.com wrote: > From: Ira Weiny > > The PKRS MSR is defined as a per-logical-processor register. This > isolates memory access by logical CPU. Unfortunately, the MSR is not > managed by XSAVE. Therefore, tasks must save/restore the MSR value on > context switch. > > Define a saved PKRS value in the task struct, as well as a cached > per-logical-processor MSR value which mirrors the MSR value of the > current CPU. Initialize all tasks with the default MSR value. Then, on > schedule in, check the saved task MSR vs the per-cpu value. If > different proceed to write the MSR. If not avoid the overhead of the > MSR write and continue. It's probably nice to note how the WRMSR is special here, in addition to the comments below. > #endif /*_ASM_X86_PKEYS_INTERNAL_H */ > diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h > index 97143d87994c..da2381136b2d 100644 > --- a/arch/x86/include/asm/processor.h > +++ b/arch/x86/include/asm/processor.h > @@ -18,6 +18,7 @@ struct vm86; > #include > #include > #include > +#include > #include > #include > #include > @@ -542,6 +543,11 @@ struct thread_struct { > > unsigned int sig_on_uaccess_err:1; > > +#ifdef CONFIG_ARCH_HAS_SUPERVISOR_PKEYS > + /* Saved Protection key register for supervisor mappings */ > + u32 saved_pkrs; > +#endif Could you take a look around thread_struct and see if there are some other MSRs near which you can stash this? This seems like a bit of a lonely place. ... > void flush_thread(void) > { > struct task_struct *tsk = current; > @@ -195,6 +212,8 @@ void flush_thread(void) > memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); > > fpu__clear_all(&tsk->thread.fpu); > + > + pks_init_task(tsk); > } > > void disable_TSC(void) > @@ -644,6 +663,8 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p) > > if ((tifp ^ tifn) & _TIF_SLD) > switch_to_sld(tifn); > + > + pks_sched_in(); > } > > /* > diff --git a/arch/x86/mm/pkeys.c b/arch/x86/mm/pkeys.c > index 3cf8f775f36d..30f65dd3d0c5 100644 > --- a/arch/x86/mm/pkeys.c > +++ b/arch/x86/mm/pkeys.c > @@ -229,3 +229,31 @@ u32 update_pkey_val(u32 pk_reg, int pkey, unsigned int flags) > > return pk_reg; > } > + > +DEFINE_PER_CPU(u32, pkrs_cache); > + > +/** > + * It should also be noted that the underlying WRMSR(MSR_IA32_PKRS) is not > + * serializing but still maintains ordering properties similar to WRPKRU. > + * The current SDM section on PKRS needs updating but should be the same as > + * that of WRPKRU. So to quote from the WRPKRU text: > + * > + * WRPKRU will never execute transiently. Memory accesses > + * affected by PKRU register will not execute (even transiently) > + * until all prior executions of WRPKRU have completed execution > + * and updated the PKRU register. > + */ > +void write_pkrs(u32 new_pkrs) > +{ > + u32 *pkrs; > + > + if (!static_cpu_has(X86_FEATURE_PKS)) > + return; > + > + pkrs = get_cpu_ptr(&pkrs_cache); > + if (*pkrs != new_pkrs) { > + *pkrs = new_pkrs; > + wrmsrl(MSR_IA32_PKRS, new_pkrs); > + } > + put_cpu_ptr(pkrs); > +} > It bugs me a *bit* that this is being called in a preempt-disabled region, but we still bother with the get/put_cpu jazz. Are there other future call-sites for this that aren't in preempt-disabled regions?