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Wed, 17 Jun 2020 04:37:42 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jlWNx-0007TR-H0; Wed, 17 Jun 2020 04:37:41 -0700 From: Srinivas Neeli To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com, sgoud@xilinx.com Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@xilinx.com Subject: [PATCH V4 4/7] gpio: zynq: Add Versal support Date: Wed, 17 Jun 2020 17:07:24 +0530 Message-Id: <1592393847-1415-5-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592393847-1415-1-git-send-email-srinivas.neeli@xilinx.com> References: <1592393847-1415-1-git-send-email-srinivas.neeli@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(136003)(39860400002)(396003)(376002)(346002)(46966005)(26005)(316002)(107886003)(2906002)(186003)(8936002)(7696005)(966005)(9786002)(5660300002)(478600001)(336012)(82740400003)(4326008)(47076004)(70586007)(70206006)(2616005)(426003)(83380400001)(36756003)(44832011)(356005)(6636002)(8676002)(82310400002)(6666004)(81166007);DIR:OUT;SFP:1101; X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a45fc6e4-536e-4360-0661-08d812b2dd5c X-MS-TrafficTypeDiagnostic: DM6PR02MB4604: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-Forefront-PRVS: 04371797A5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oYp0rXqZrvBcTPyJaRJc9hxUTc9UCNJigroDCgDZJnU8iM/YcHEpTv+lFJ7Qh4pgd8j/t3qUbmDNpBwCI3VwF0zzjsHAeMeSIxAXDZIGHrgwhu4LNcD7LWEa+7vV1TkLlGqnrdAWOxxyDbzDcwTv3CzHi5R+NSfRx/xsYjgDjwlb73lNqqzSLqgRRrrgW09fytamJWCZH8zyN2WFpkk9/h6xDp00X6oR/Owb2fJZNo6XL7JgXmrcYkeLpnl6J/ZI1sgoUydvDlAiUUC5VnmiG9tWK7vZ2KuluPZrG26tdJLUGnZjKt8PRSxjfmKqSwRsVXpJgTIqMD62b+VsqecRzlvdyFwwtlMFMeq3bPP6ljBgr5XRn4qHc+03S5yTy3RE/YK4wBCUKnsm4fpVq7UB4cBPQtYYz9tv5iKO4GdIbFVfVY2KyyVyUBU+kjpU6IGwCk2zrsj/tFZkoLbhOgktF2RzjyBi8UxW0/UIv+iaHbM= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2020 11:37:50.0129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a45fc6e4-536e-4360-0661-08d812b2dd5c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4604 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Shubhrajyoti Datta Add Versal support in gpio. Only bank 0 and 3 are connected to the Multiplexed Input output pins. Bank 0 to mio and bank3 to fabric Multiplexed input output pins. Versal devices are the industry's first adaptive compute acceleration platforms. https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf On the Versal platform, we are using two customized GPIO controllers(IP) which were used in Zynq/ZynqMp platform. One of them present in the Platform Management Controller(PMC) block and other in Processing System(PS) block. In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only Bank 0 & 3 are enabled. You can find more details of GPIO IP in ZynqMP TRM General Purpose I/O(Chapter-27). https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Signed-off-by: Shubhrajyoti Datta Signed-off-by: Michal Simek --- drivers/gpio/gpio-zynq.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index fb93b35ab19e..9ac69144a0eb 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -22,6 +22,8 @@ /* Maximum banks */ #define ZYNQ_GPIO_MAX_BANK 4 #define ZYNQMP_GPIO_MAX_BANK 6 +#define VERSAL_GPIO_MAX_BANK 4 +#define VERSAL_UNUSED_BANKS 2 #define ZYNQ_GPIO_BANK0_NGPIO 32 #define ZYNQ_GPIO_BANK1_NGPIO 22 @@ -96,6 +98,7 @@ /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) #define GPIO_QUIRK_DATA_RO_BUG BIT(1) +#define GPIO_QUIRK_VERSAL BIT(2) struct gpio_regs { u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; @@ -199,6 +202,8 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, gpio->p_data->bank_min[bank]; return; } + if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) + bank = bank + VERSAL_UNUSED_BANKS; } /* default */ @@ -656,6 +661,8 @@ static void zynq_gpio_irqhandler(struct irq_desc *desc) int_enb = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); + if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) + bank_num = bank_num + VERSAL_UNUSED_BANKS; } chained_irq_exit(irqchip, desc); @@ -685,6 +692,8 @@ static void zynq_gpio_save_context(struct zynq_gpio *gpio) gpio->context.int_any[bank_num] = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); + if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) + bank_num = bank_num + VERSAL_UNUSED_BANKS; } } @@ -716,6 +725,8 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio) writel_relaxed(~(gpio->context.int_en[bank_num]), gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); + if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) + bank_num = bank_num + VERSAL_UNUSED_BANKS; } } @@ -787,6 +798,17 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { zynq_gpio_runtime_resume, NULL) }; +static const struct zynq_platform_data versal_gpio_def = { + .label = "versal_gpio", + .quirks = GPIO_QUIRK_VERSAL, + .ngpio = 58, + .max_bank = VERSAL_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ + .bank_min[3] = 26, + .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ +}; + static const struct zynq_platform_data zynqmp_gpio_def = { .label = "zynqmp_gpio", .quirks = GPIO_QUIRK_DATA_RO_BUG, @@ -824,6 +846,7 @@ static const struct zynq_platform_data zynq_gpio_def = { static const struct of_device_id zynq_gpio_of_match[] = { { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, + { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, { /* end of table */ } }; MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); @@ -903,9 +926,12 @@ static int zynq_gpio_probe(struct platform_device *pdev) goto err_pm_dis; /* disable interrupts for all banks */ - for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); + if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) + bank_num = bank_num + VERSAL_UNUSED_BANKS; + } /* Set up the GPIO irqchip */ girq = &chip->irq; -- 2.7.4