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* Re: [PATCH v2] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
       [not found] <20200720092328.708-1-yuzenghui@huawei.com>
@ 2020-07-25 14:23 ` Marc Zyngier
  0 siblings, 0 replies; only message in thread
From: Marc Zyngier @ 2020-07-25 14:23 UTC (permalink / raw)
  To: Jason Cooper, Alexandre Torgue, Thomas Gleixner, Zenghui Yu,
	linux-kernel
  Cc: linux-gpio, marex, linux-stm32, linux-arm-kernel, stable,
	wanghaibin.wang

On Mon, 20 Jul 2020 17:23:28 +0800, Zenghui Yu wrote:
> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
> register-based invalidation operation for a vPEID not mapped to that RD,
> or another RD within the same CommonLPIAff group.
> 
> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
> exclusion between vPE affinity change and RD access") tried to address the
> race between the RD accesses and the vPE affinity change, but somehow
> forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
> evaluating vpe->col_idx to fix it.

Applied to irq/irqchip-5.9, thanks!

[1/1] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
      commit: fdccf1d9d10395abfe082f50694f374997c6e101

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.



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     [not found] <20200720092328.708-1-yuzenghui@huawei.com>
2020-07-25 14:23 ` [PATCH v2] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR Marc Zyngier

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