From: Stephen Boyd <swboyd@chromium.org>
To: Douglas Anderson <dianders@chromium.org>,
Jason Cooper <jason@lakedaemon.net>,
Linus Walleij <linus.walleij@linaro.org>,
Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
Maulik Shah <mkshah@codeaurora.org>,
linux-arm-msm@vger.kernel.org,
Srinivas Ramana <sramana@codeaurora.org>,
Neeraj Upadhyay <neeraju@codeaurora.org>,
linux-gpio@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>,
Andy Gross <agross@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 3/4] pinctrl: qcom: Don't clear pending interrupts when enabling
Date: Wed, 16 Dec 2020 20:54:47 -0800 [thread overview]
Message-ID: <160818088793.1580929.1672018770454181938@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20201211141514.v4.3.I7cf3019783720feb57b958c95c2b684940264cd1@changeid>
Quoting Douglas Anderson (2020-12-11 14:15:37)
> In Linux, if a driver does disable_irq() and later does enable_irq()
> on its interrupt, I believe it's expecting these properties:
> * If an interrupt was pending when the driver disabled then it will
> still be pending after the driver re-enables.
> * If an edge-triggered interrupt comes in while an interrupt is
> disabled it should assert when the interrupt is re-enabled.
>
> If you think that the above sounds a lot like the disable_irq() and
> enable_irq() are supposed to be masking/unmasking the interrupt
> instead of disabling/enabling it then you've made an astute
> observation. Specifically when talking about interrupts, "mask"
> usually means to stop posting interrupts but keep tracking them and
> "disable" means to fully shut off interrupt detection. It's
> unfortunate that this is so confusing, but presumably this is all the
> way it is for historical reasons.
>
> Perhaps more confusing than the above is that, even though clients of
> IRQs themselves don't have a way to request mask/unmask
> vs. disable/enable calls, IRQ chips themselves can implement both.
> ...and yet more confusing is that if an IRQ chip implements
> disable/enable then they will be called when a client driver calls
> disable_irq() / enable_irq().
>
> It does feel like some of the above could be cleared up. However,
> without any other core interrupt changes it should be clear that when
> an IRQ chip gets a request to "disable" an IRQ that it has to treat it
> like a mask of that IRQ.
>
> In any case, after that long interlude you can see that the "unmask
> and clear" can break things. Maulik tried to fix it so that we no
> longer did "unmask and clear" in commit 71266d9d3936 ("pinctrl: qcom:
> Move clearing pending IRQ to .irq_request_resources callback"), but it
> only handled the PDC case (it also had problems, but that's the
> subject of another patch). Let's fix this for the non-PDC case.
>
> From my understanding the source of the phantom interrupt in the
> non-PDC case was the one that could have been introduced in
> msm_gpio_irq_set_type(). Let's handle that one and then get rid of
> the clear.
>
> Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio")
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
One comment clarification below.
> I don't have lots of good test cases here, so hopefully someone from
> Qualcomm can confirm that this works well for them and there isn't
> some other phantom interrupt source that I'm not aware of.
>
> Changes in v4:
> - ("pinctrl: qcom: Don't clear pending interrupts when enabling") split for v4.
>
> drivers/pinctrl/qcom/pinctrl-msm.c | 32 +++++++++++++-----------------
> 1 file changed, 14 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 588df91274e2..f785646d1df7 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -1046,6 +1032,16 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> }
> msm_writel_intr_cfg(val, pctrl, g);
>
> + /*
> + * The first time we set RAW_STATUS_EN it could trigger an interrupt.
> + * Clear it. This is safe because we have IRQCHIP_SET_TYPE_MASKED.
Clear the interrupt? 'it' is ambiguous.
> + */
> + if (!was_enabled) {
> + val = msm_readl_intr_status(pctrl, g);
> + val &= ~BIT(g->intr_status_bit);
> + msm_writel_intr_status(val, pctrl, g);
> + }
> +
> if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
> msm_gpio_update_dual_edge_pos(pctrl, g, d);
>
next prev parent reply other threads:[~2020-12-17 4:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 22:15 [PATCH v4 1/4] irqchip: qcom-pdc: Fix phantom irq when changing between rising/falling Douglas Anderson
2020-12-11 22:15 ` [PATCH v4 2/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Douglas Anderson
2020-12-11 22:15 ` [PATCH v4 3/4] pinctrl: qcom: Don't clear pending interrupts when enabling Douglas Anderson
2020-12-17 4:54 ` Stephen Boyd [this message]
2020-12-18 5:35 ` Rajendra Nayak
2020-12-21 16:00 ` Maulik Shah
2021-01-08 17:37 ` Doug Anderson
2020-12-11 22:15 ` [PATCH v4 4/4] pinctrl: qcom: Clear possible pending parent irq when remuxing GPIOs Douglas Anderson
2020-12-12 10:48 ` (subset) [PATCH v4 1/4] irqchip: qcom-pdc: Fix phantom irq when changing between rising/falling Marc Zyngier
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