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From: Stephen Boyd <swboyd@chromium.org>
To: Douglas Anderson <dianders@chromium.org>,
	Jason Cooper <jason@lakedaemon.net>,
	Linus Walleij <linus.walleij@linaro.org>,
	Marc Zyngier <maz@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
	Neeraj Upadhyay <neeraju@codeaurora.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	Maulik Shah <mkshah@codeaurora.org>,
	linux-gpio@vger.kernel.org,
	Srinivas Ramana <sramana@codeaurora.org>,
	linux-arm-msm@vger.kernel.org,
	Douglas Anderson <dianders@chromium.org>,
	Andy Gross <agross@kernel.org>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 2/4] pinctrl: qcom: No need to read-modify-write the interrupt status
Date: Wed, 13 Jan 2021 23:01:54 -0800	[thread overview]
Message-ID: <161060771402.3661239.1174238618385699475@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210108093339.v5.2.I3635de080604e1feda770591c5563bd6e63dd39d@changeid>

Quoting Douglas Anderson (2021-01-08 09:35:14)
> When the Qualcomm pinctrl driver wants to Ack an interrupt, it does a
> read-modify-write on the interrupt status register.  On some SoCs it
> makes sure that the status bit is 1 to "Ack" and on others it makes
> sure that the bit is 0 to "Ack".  Presumably the first type of
> interrupt controller is a "write 1 to clear" type register and the
> second just let you directly set the interrupt status register.
> 
> As far as I can tell from scanning structure definitions, the
> interrupt status bit is always in a register by itself.  Thus with
> both types of interrupt controllers it is safe to "Ack" interrupts
> without doing a read-modify-write.  We can do a simple write.
> 
> It should be noted that if the interrupt status bit _was_ ever in a
> register with other things (like maybe status bits for other GPIOs):
> a) For "write 1 clear" type controllers then read-modify-write would
>    be totally wrong because we'd accidentally end up clearing
>    interrupts we weren't looking at.
> b) For "direct set" type controllers then read-modify-write would also
>    be wrong because someone setting one of the other bits in the
>    register might accidentally clear (or set) our interrupt.
> I say this simply to show that the current read-modify-write doesn't
> provide any sort of "future proofing" of the code.  In fact (for
> "write 1 clear" controllers) the new code is slightly more "future
> proof" since it would allow more than one interrupt status bits to
> share a register.
> 
> NOTE: this code fixes no bugs--it simply avoids an extra register
> read.
> 
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

  parent reply	other threads:[~2021-01-14  7:02 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-08 17:35 [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Douglas Anderson
2021-01-08 17:35 ` [PATCH v5 2/4] pinctrl: qcom: No need to read-modify-write the interrupt status Douglas Anderson
2021-01-11 15:58   ` Maulik Shah
2021-01-14  7:01   ` Stephen Boyd [this message]
2021-01-14 16:33   ` Bjorn Andersson
2021-01-08 17:35 ` [PATCH v5 3/4] pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmasking Douglas Anderson
2021-01-11 15:59   ` Maulik Shah
2021-01-14  7:03   ` Stephen Boyd
2021-01-14 16:34   ` Bjorn Andersson
2021-01-08 17:35 ` [PATCH v5 4/4] pinctrl: qcom: Don't clear pending interrupts when enabling Douglas Anderson
2021-01-09  0:36   ` Linus Walleij
2021-01-16  1:04     ` Doug Anderson
2021-01-11 16:01   ` Maulik Shah
2021-01-14  7:14   ` Stephen Boyd
2021-01-14 17:07     ` Bjorn Andersson
2021-01-14 17:15     ` Bjorn Andersson
2021-01-14 17:58       ` Doug Anderson
2021-01-14 17:58     ` Doug Anderson
2021-01-14 21:04       ` Stephen Boyd
2021-01-11 15:56 ` [PATCH v5 1/4] pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 Maulik Shah
2021-01-14 16:32 ` Bjorn Andersson

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