* [gpio:devel-cleanup-irqchip 60/60] drivers/pinctrl/intel/pinctrl-cherryview.c:1632:8: error: 'struct gpio_irq_chip' has no member named 'default_handler'; did you mean 'default_type'?
@ 2019-09-06 13:57 kbuild test robot
0 siblings, 0 replies; only message in thread
From: kbuild test robot @ 2019-09-06 13:57 UTC (permalink / raw)
To: Linus Walleij; +Cc: kbuild-all, linux-gpio
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tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-gpio.git devel-cleanup-irqchip
head: 42266e389e3816d6302149aa23d62b0e41964851
commit: 42266e389e3816d6302149aa23d62b0e41964851 [60/60] RFC: pinctrl: cherryview: Pass irqchip when adding gpiochip
config: i386-randconfig-e004-201935 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
git checkout 42266e389e3816d6302149aa23d62b0e41964851
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pinctrl/intel/pinctrl-cherryview.c: In function 'chv_gpio_probe':
>> drivers/pinctrl/intel/pinctrl-cherryview.c:1632:8: error: 'struct gpio_irq_chip' has no member named 'default_handler'; did you mean 'default_type'?
girq->default_handler = IRQ_TYPE_NONE;
^~~~~~~~~~~~~~~
default_type
vim +1632 drivers/pinctrl/intel/pinctrl-cherryview.c
1545
1546 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1547 {
1548 const struct chv_gpio_pinrange *range;
1549 struct gpio_chip *chip = &pctrl->chip;
1550 struct gpio_irq_chip *girq;
1551 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1552 const struct chv_community *community = pctrl->community;
1553 int ret, i, irq_base;
1554
1555 *chip = chv_gpio_chip;
1556
1557 chip->ngpio = community->pins[community->npins - 1].number + 1;
1558 chip->label = dev_name(pctrl->dev);
1559 chip->parent = pctrl->dev;
1560 chip->base = -1;
1561 chip->irq.need_valid_mask = need_valid_mask;
1562
1563 for (i = 0; i < community->ngpio_ranges; i++) {
1564 range = &community->gpio_ranges[i];
1565 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1566 range->base, range->base,
1567 range->npins);
1568 if (ret) {
1569 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1570 return ret;
1571 }
1572 }
1573
1574 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1575 for (i = 0; i < community->npins; i++) {
1576 const struct pinctrl_pin_desc *desc;
1577 u32 intsel;
1578
1579 desc = &community->pins[i];
1580
1581 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1582 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1583 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1584
1585 if (need_valid_mask && intsel >= community->nirqs)
1586 clear_bit(i, chip->irq.valid_mask);
1587 }
1588
1589 /*
1590 * The same set of machines in chv_no_valid_mask[] have incorrectly
1591 * configured GPIOs that generate spurious interrupts so we use
1592 * this same list to apply another quirk for them.
1593 *
1594 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1595 */
1596 if (!need_valid_mask) {
1597 /*
1598 * Mask all interrupts the community is able to generate
1599 * but leave the ones that can only generate GPEs unmasked.
1600 */
1601 chv_writel(GENMASK(31, pctrl->community->nirqs),
1602 pctrl->regs + CHV_INTMASK);
1603 }
1604
1605 /* Clear all interrupts */
1606 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1607
1608 /*
1609 * FIXME: this picks as many IRQs as there are lines in the
1610 * "community", which is then later associated per-range below
1611 * registering the gpio_chip. This is actually hierarchical IRQ.
1612 */
1613 if (!need_valid_mask) {
1614 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1615 community->npins, NUMA_NO_NODE);
1616 if (irq_base < 0) {
1617 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1618 return irq_base;
1619 }
1620 }
1621
1622 girq = &chip->irq;
1623 girq->chip = &chv_gpio_irqchip;
1624 girq->parent_handler = chv_gpio_irq_handler;
1625 girq->num_parents = 1;
1626 girq->parents = devm_kcalloc(pctrl->dev, 1,
1627 sizeof(*girq->parents),
1628 GFP_KERNEL);
1629 if (!girq->parents)
1630 return -ENOMEM;
1631 girq->parents[0] = irq;
> 1632 girq->default_handler = IRQ_TYPE_NONE;
1633 girq->handler = handle_bad_irq;
1634
1635 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1636 if (ret) {
1637 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1638 return ret;
1639 }
1640
1641 /*
1642 * FIXME: this associates a different IRQ with each discrete range
1643 * inside the community. If we use the hierarchical irq support,
1644 * the .translate() function can do this translation for each IRQ.
1645 */
1646 if (!need_valid_mask) {
1647 for (i = 0; i < community->ngpio_ranges; i++) {
1648 range = &community->gpio_ranges[i];
1649
1650 irq_domain_associate_many(chip->irq.domain, irq_base,
1651 range->base, range->npins);
1652 irq_base += range->npins;
1653 }
1654 }
1655
1656 return 0;
1657 }
1658
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