From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-gpio@vger.kernel.org,
Mika Westerberg <mika.westerberg@linux.intel.com>,
ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH v3 1/2] gpio: sch: Add edge event support
Date: Fri, 22 Nov 2019 13:12:19 +0200 [thread overview]
Message-ID: <20191122111219.GW32742@smile.fi.intel.com> (raw)
In-Reply-To: <42ae6149a14f81fd86c5acb5bd33e987123b6bed.1574277614.git.jan.kiszka@siemens.com>
On Wed, Nov 20, 2019 at 08:20:13PM +0100, Jan Kiszka wrote:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Add the required infrastructure consisting of an irq_chip_generic with
> its irq_chip_type callbacks to enable and report edge events of the pins
> to the gpio core. The actual hook-up of the event interrupt will happen
> separately.
> +static int sch_irq_type(struct irq_data *d, unsigned int type)
> +{
> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> + struct sch_gpio *sch = gc->private;
> + unsigned int gpio_num = d->irq - sch->irq_base;
> + unsigned long flags;
> + int rising = 0;
> + int falling = 0;
> +
> + switch (type & IRQ_TYPE_SENSE_MASK) {
> + case IRQ_TYPE_EDGE_RISING:
> + rising = 1;
> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + falling = 1;
> + break;
> + case IRQ_TYPE_EDGE_BOTH:
> + rising = 1;
> + falling = 1;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + spin_lock_irqsave(&sch->lock, flags);
> + sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
> + sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
> + spin_unlock_irqrestore(&sch->lock, flags);
Won't we need to set up IRQ handler here and use handle_bad_irq() during
initialization phase?
> +
> + return 0;
> +}
> + irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, sch->chip.ngpio,
> + NUMA_NO_NODE);
> + if (irq_base < 0)
> + return irq_base;
> + sch->irq_base = irq_base;
> +
> + gc = devm_irq_alloc_generic_chip(&pdev->dev, "sch_gpio", 1, irq_base,
> + NULL, handle_simple_irq);
> + if (!gc)
> + return -ENOMEM;
> +
> + gc->private = sch;
> + ct = gc->chip_types;
> +
> + ct->chip.irq_mask = sch_irq_mask;
> + ct->chip.irq_unmask = sch_irq_unmask;
> + ct->chip.irq_set_type = sch_irq_type;
> +
> + ret = devm_irq_setup_generic_chip(&pdev->dev, gc,
> + IRQ_MSK(sch->chip.ngpio),
> + 0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
> + if (ret)
> + return ret;
Shan't we do this in the (similar) way how it's done in pinctrl-cherryview.c
driver? (Keep in mind later patches which are going to be v5.5)
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2019-11-22 11:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-20 19:20 [PATCH v3 0/2] gpio: sch: Interrupt support Jan Kiszka
2019-11-20 19:20 ` [PATCH v3 1/2] gpio: sch: Add edge event support Jan Kiszka
2019-11-22 10:41 ` Mika Westerberg
2019-11-22 11:12 ` Andy Shevchenko [this message]
2019-11-22 15:33 ` Jan Kiszka
2019-12-09 16:36 ` Andy Shevchenko
2019-11-28 9:33 ` Linus Walleij
2019-11-20 19:20 ` [PATCH v3 2/2] gpio: sch: Hook into ACPI SCI handler to catch GPIO edge events Jan Kiszka
2019-11-22 10:43 ` Mika Westerberg
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