From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E3EC2D0EE for ; Tue, 31 Mar 2020 16:29:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E76DD20658 for ; Tue, 31 Mar 2020 16:29:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731238AbgCaQ33 (ORCPT ); Tue, 31 Mar 2020 12:29:29 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:47221 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730011AbgCaQ33 (ORCPT ); Tue, 31 Mar 2020 12:29:29 -0400 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jJJlN-0007Xk-7h; Tue, 31 Mar 2020 18:29:17 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1jJJlK-0005tF-Br; Tue, 31 Mar 2020 18:29:14 +0200 Date: Tue, 31 Mar 2020 18:29:14 +0200 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: Russell King - ARM Linux admin Cc: Mark Rutland , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Linus Walleij , linux-pwm@vger.kernel.org, Bartosz Golaszewski , Rob Herring , Thierry Reding , linux-gpio@vger.kernel.org, Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth , kernel@pengutronix.de Subject: Re: [PATCH RFC 2/6] gpio: mvebu: honour EPROBE_DEFER for devm_clk_get() Message-ID: <20200331162914.h65jnclbsmlzpzti@pengutronix.de> References: <20200329104549.GX25745@shell.armlinux.org.uk> <20200329131659.4hbshjst4ccvje2n@pengutronix.de> <20200329133400.GA25745@shell.armlinux.org.uk> <20200329180056.cwju3zqviwnwwjd6@pengutronix.de> <20200329182236.GC25745@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200329182236.GC25745@shell.armlinux.org.uk> User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-gpio@vger.kernel.org Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hello Russell, On Sun, Mar 29, 2020 at 07:22:36PM +0100, Russell King - ARM Linux admin wrote: > On Sun, Mar 29, 2020 at 08:00:56PM +0200, Uwe Kleine-König wrote: > > On Sun, Mar 29, 2020 at 02:34:00PM +0100, Russell King - ARM Linux admin wrote: > > > On Sun, Mar 29, 2020 at 03:16:59PM +0200, Uwe Kleine-König wrote: > > > > On Sun, Mar 29, 2020 at 11:48:09AM +0100, Russell King wrote: > > > > > diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c > > > > > index fa5641615db6..ee13b11c5298 100644 > > > > > --- a/drivers/gpio/gpio-mvebu.c > > > > > +++ b/drivers/gpio/gpio-mvebu.c > > > > > @@ -1132,6 +1132,9 @@ static int mvebu_gpio_probe(struct platform_device *pdev) > > > > > } > > > > > > > > > > mvchip->clk = devm_clk_get(&pdev->dev, NULL); > > > > > + if (mvchip->clk == ERR_PTR(-EPROBE_DEFER)) > > > > > + return -EPROBE_DEFER; > > > > > + > > > > > /* Not all SoCs require a clock.*/ > > > > > if (!IS_ERR(mvchip->clk)) > > > > > clk_prepare_enable(mvchip->clk); > > > > > > > > I'd say the following is the right thing to do here: > > > > > > > > mvchip->clk = devm_clk_get_optional(...); > > > > if (IS_ERR(mvchip->clk)) > > > > return ... > > > > > > It's not that simple. The clock is required for Armada 370, and is > > > optional for Armada 8040. > > > > I'd say it is still the right approach here. On Armada 370 the dtb then > > has a clk and on Armada 8040 it doesn't. So if with > > devm_clk_get_optional() something goes wrong that's because the dtb is > > wrong. And in fact the handling is even better than with your suggested > > patch as every error (but EPROBE_DEFER) is ignored instead of passed to > > the caller with your (and the existing) approach. > > Sort of. Every error is currently treated as "no clock", and only > later does such an error become fatal in the driver _if_ PWM is > configured into the kernel and we're running on Armada 370. If PWM > is disabled in the kernel, or on some other SoC, then the driver > doesn't care whether getting the clock reported any kind of error. > > Your proposal is to always treat any error getting the clock, > irrespective of whether there is PWM or not, as a fatal error for > the driver. Is this clock (assuming it's available) needed for GPIO operation? If not, I'd say the call to devm_clk_get should go into mvebu_pwm_probe(). And if yes, then use devm_clk_get_optional in mvebu_gpio_probe() and either request it once more in mvebu_pwm_probe() (without _optional) or test for mvchip->clk == NULL. (Or maybe just don't check and let the driver fail when clk_get_rate(mvchip->clk) returns zero.) > That is an entirely seperate functional change. This is still different to what you do, but it is (IMHO) cleaner and fixes the problem you want to solve en passant. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |