From: Abanoub Sameh <abanoubsameh8@gmail.com>
To: andy.shevchenko@gmail.com
Cc: linus.walleij@linaro.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org,
Abanoub Sameh <abanoubsameh@protonmail.com>
Subject: [PATCH 3/7] gpio: fixed coding style issues in gpio-intel-mid.c
Date: Tue, 21 Jul 2020 11:35:18 +0200 [thread overview]
Message-ID: <20200721093522.2309530-3-abanoubsameh@protonmail.com> (raw)
In-Reply-To: <20200721093522.2309530-1-abanoubsameh@protonmail.com>
Signed-off-by: Abanoub Sameh <abanoubsameh@protonmail.com>
---
drivers/gpio/gpio-intel-mid.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-intel-mid.c b/drivers/gpio/gpio-intel-mid.c
index 86a10c808ef6..a609964645c1 100644
--- a/drivers/gpio/gpio-intel-mid.c
+++ b/drivers/gpio/gpio-intel-mid.c
@@ -38,7 +38,7 @@
* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
*
* so the bit of reg_addr is to control pin offset's GPDR feature
-*/
+ */
enum GPIO_REG {
GPLR = 0, /* pin level read-only */
@@ -64,27 +64,27 @@ struct intel_mid_gpio {
struct pci_dev *pdev;
};
-static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
+static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
enum GPIO_REG reg_type)
{
struct intel_mid_gpio *priv = gpiochip_get_data(chip);
- unsigned nreg = chip->ngpio / 32;
+ unsigned int nreg = chip->ngpio / 32;
u8 reg = offset / 32;
return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}
-static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
+static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned int offset,
enum GPIO_REG reg_type)
{
struct intel_mid_gpio *priv = gpiochip_get_data(chip);
- unsigned nreg = chip->ngpio / 32;
+ unsigned int nreg = chip->ngpio / 32;
u8 reg = offset / 16;
return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}
-static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
+static int intel_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
u32 value = readl(gafr);
@@ -97,14 +97,14 @@ static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
return 0;
}
-static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *gplr = gpio_reg(chip, offset, GPLR);
return !!(readl(gplr) & BIT(offset % 32));
}
-static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
void __iomem *gpsr, *gpcr;
@@ -117,7 +117,7 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
}
}
-static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct intel_mid_gpio *priv = gpiochip_get_data(chip);
void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
@@ -140,7 +140,7 @@ static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
}
static int intel_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
+ unsigned int offset, int value)
{
struct intel_mid_gpio *priv = gpiochip_get_data(chip);
void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
@@ -163,7 +163,7 @@ static int intel_gpio_direction_output(struct gpio_chip *chip,
return 0;
}
-static int intel_mid_irq_type(struct irq_data *d, unsigned type)
+static int intel_mid_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_mid_gpio *priv = gpiochip_get_data(gc);
@@ -297,7 +297,7 @@ static int intel_mid_irq_init_hw(struct gpio_chip *chip)
{
struct intel_mid_gpio *priv = gpiochip_get_data(chip);
void __iomem *reg;
- unsigned base;
+ unsigned int base;
for (base = 0; base < priv->chip.ngpio; base += 32) {
/* Clear the rising-edge detect register */
@@ -317,6 +317,7 @@ static int intel_mid_irq_init_hw(struct gpio_chip *chip)
static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
{
int err = pm_schedule_suspend(dev, 500);
+
return err ?: -EBUSY;
}
--
2.28.0.rc0
next prev parent reply other threads:[~2020-07-21 9:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-21 9:35 [PATCH 1/7] gpio: fixed coding style issues in gpio-crystalcove.c Abanoub Sameh
2020-07-21 9:35 ` [PATCH 2/7] gpio: fixed coding style issues in gpio-ich.c Abanoub Sameh
2020-07-21 9:35 ` Abanoub Sameh [this message]
2020-07-21 9:35 ` [PATCH 4/7] gpio: fixed coding style issues in gpio-ml-ioh.c Abanoub Sameh
2020-07-21 9:35 ` [PATCH 5/7] gpio: fixed coding style issues in gpio-msic.c Abanoub Sameh
2020-07-21 9:35 ` [PATCH 6/7] gpio: fixed coding style issues in gpio-pch.c Abanoub Sameh
2020-07-21 9:35 ` [PATCH 7/7] gpio: fixed coding style issues in gpio-sch.c Abanoub Sameh
2020-07-21 10:50 ` [PATCH 1/7] gpio: fixed coding style issues in gpio-crystalcove.c Andy Shevchenko
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