From: Lars Povlsen <lars.povlsen@microchip.com>
To: SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
Olof Johansson <olof@lixom.net>,
"Michael Turquette" <mturquette@baylibre.com>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: [PATCH v4 09/10] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
Date: Mon, 27 Jul 2020 10:42:10 +0200 [thread overview]
Message-ID: <20200727084211.6632-10-lars.povlsen@microchip.com> (raw)
In-Reply-To: <20200727084211.6632-1-lars.povlsen@microchip.com>
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 39 +++++++++++++----------
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index baf4176ce1dfe..161846caf9c94 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -72,20 +72,29 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
- clocks: clocks {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- ahb_clk: ahb-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
- sys_clk: sys-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <625000000>;
- };
+ lcpll_clk: lcpll-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500000000>;
+ };
+
+ clks: clock-controller@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ clocks = <&lcpll_clk>;
+ reg = <0x6 0x1110000c 0x24>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <625000000>;
};
axi: axi@600000000 {
@@ -161,8 +170,6 @@ uart2_pins: uart2-pins {
pins = "GPIO_26", "GPIO_27";
function = "uart2";
};
-
};
-
};
};
--
2.27.0
next prev parent reply other threads:[~2020-07-27 8:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-27 8:42 [PATCH v4 00/10] Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 01/10] dt-bindings: arm: sparx5: Add documentation " Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 02/10] arm64: sparx5: Add support for Microchip 2xA53 SoC Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 03/10] arm64: dts: sparx5: Add basic cpu support Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 04/10] arm64: dts: sparx5: Add pinctrl support Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 05/10] pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 06/10] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 07/10] dt-bindings: clock: sparx5: Add bindings include file Lars Povlsen
2020-07-27 8:42 ` [PATCH v4 08/10] clk: sparx5: Add Sparx5 SoC DPLL clock driver Lars Povlsen
2020-07-27 8:42 ` Lars Povlsen [this message]
2020-07-27 8:42 ` [PATCH v4 10/10] arm64: dts: sparx5: Add i2c devices, i2c muxes Lars Povlsen
2020-07-27 9:50 ` [PATCH v4 00/10] Adding support for Microchip Sparx5 SoC Alexandre Belloni
2020-07-27 10:29 ` Lars Povlsen
2020-07-27 11:07 ` Arnd Bergmann
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