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Mon, 17 Aug 2020 12:48:34 -0700 (PDT) Received: from xps15 ([64.188.179.249]) by smtp.gmail.com with ESMTPSA id d12sm5500906ilq.34.2020.08.17.12.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2020 12:48:34 -0700 (PDT) Received: (nullmailer pid 1435985 invoked by uid 1000); Mon, 17 Aug 2020 19:48:33 -0000 Date: Mon, 17 Aug 2020 13:48:33 -0600 From: Rob Herring To: Nobuhiro Iwamatsu Cc: Linus Walleij , Catalin Marinas , Will Deacon , punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH 1/8] dt-bindings: pinctrl: Add bindings for Toshiba Visconti TMPV7700 SoC Message-ID: <20200817194833.GB1432385@bogus> References: <20200817014632.595898-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20200817014632.595898-2-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200817014632.595898-2-nobuhiro1.iwamatsu@toshiba.co.jp> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon, Aug 17, 2020 at 10:46:25AM +0900, Nobuhiro Iwamatsu wrote: > Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. > > Signed-off-by: Nobuhiro Iwamatsu > --- > .../pinctrl/toshiba,visconti-pinctrl.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > new file mode 100644 > index 000000000000..4009902cd396 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba Visconti TMPV770x pin mux/config controller > + > +maintainers: > + - Nobuhiro Iwamatsu > + > +description: > + Toshiba's Visconti ARM SoC a pin mux/config controller. > + > +properties: > + compatible: > + enum: > + - toshiba,tmpv7708-pinctrl > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +patternProperties: > + '^.*$': For new bindings, please define something like '-pins$' for the pin nodes. > + if: > + type: object > + then: Then we don't have to do this if/then. This also needs a $ref to the common pinctrl schemas. > + properties: > + function: > + description: > + Function to mux. > + $ref: "/schemas/types.yaml#/definitions/string" > + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, > + spi0, spi1, spi2, spi3, spi4, spi5, spi6, > + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] > + > + groups: > + description: > + Name of the pin group to use for the functions. > + $ref: "/schemas/types.yaml#/definitions/string" > + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, > + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, > + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, > + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, > + uart0_grp, uart1_grp, uart2_grp, uart3_grp, > + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, > + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, > + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, > + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, > + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, > + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] > + > + drive-strength: > + enum: [2, 4, 6, 8, 16, 24, 32] > + default: 2 > + description: > + Selects the drive strength for the specified pins, in mA. > + > + bias-pull-up: true > + > + bias-pull-down: true > + > + bias-disable: true > + > +additionalProperties: false > + > +examples: > + # Pinmux controller node > + - | > + pmux: pmux@24190000 { > + compatible = "toshiba,tmpv7708-pinctrl"; > + reg = <0 0x24190000 0 0x10000>; > + > + spi_0: spi_0 { > + function = "spi0"; > + groups = "spi0_grp"; > + }; > + }; > -- > 2.27.0 >