From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A94B4C4332F for ; Fri, 14 Oct 2022 08:23:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229560AbiJNIXp (ORCPT ); Fri, 14 Oct 2022 04:23:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229518AbiJNIXo (ORCPT ); Fri, 14 Oct 2022 04:23:44 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 495CBA98DA; Fri, 14 Oct 2022 01:23:42 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29E8NL0w091226; Fri, 14 Oct 2022 03:23:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1665735801; bh=caQP+xhdENHxbYMLUB9kynmLwJgSaibC+jH2dXJ2b7c=; h=From:To:CC:Subject:Date; b=XX0/wemrapcy1C1/flBxmKy+Im4jvtqo9DAOyL9LpQItbCMo6+PbSwI7Ps0W/SWWP rCI0M5XGqta4iMKSceD2B3N5SXvyU690p61InXpNfLaQ0NEuPypPwo3gHrq6vl92Wz ecJHhuciq6NYZ5vNHMGtbCz7tgA4wzQMfj0riCjM= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29E8NLBL066300 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 14 Oct 2022 03:23:21 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 14 Oct 2022 03:23:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 14 Oct 2022 03:23:21 -0500 Received: from LT5CD112GSQZ.ent.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29E8NFmT021645; Fri, 14 Oct 2022 03:23:16 -0500 From: Apurva Nandan To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Linus Walleij , , , , CC: Apurva Nandan , Hari Nagalla Subject: [PATCH v2 0/4] Add initial support for J784S4 SoC Date: Fri, 14 Oct 2022 13:53:10 +0530 Message-ID: <20221014082314.118361-1-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The J784S4 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some highlights of this SoC are: * Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs, 4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for deep learning and CNN. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one DPI interface. * Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, Up to 20 MCANs, among other peripherals. See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022) for further details: http://www.ti.com/lit/zip/spruj52 bootlog: https://pastebin.ubuntu.com/p/XzbP9mHkKF/plain/ Changelog: - Disabled all the IPs that are not mandatory for booting up the SoC by default in the dtsi, and thus this gives a minimal SoC boot devicetree. - Moved no-1-8-v property from the k3-j784s4-evm.dts file to k3-j784s4-main.dtsi file. - Naming changes (hwlock, regulator) and commit description changes. - Added device specific compatible for j721e system controller. - Dropped bootargs completely. Apurva Nandan (4): dt-bindings: arm: ti: Add bindings for J784s4 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4 arm64: dts: ti: Add initial support for J784S4 SoC arm64: dts: ti: Add support for J784S4 EVM board .../devicetree/bindings/arm/ti/k3.yaml | 6 + arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 199 ++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1010 +++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 318 ++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 287 +++++ include/dt-bindings/pinctrl/k3.h | 3 + 7 files changed, 1825 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4.dtsi -- 2.17.1