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From: Icenowy Zheng <uwu@icenowy.me>
To: Hal Feng <hal.feng@linux.starfivetech.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Emil Renner Berthing <kernel@esmil.dk>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings
Date: Thu, 20 Oct 2022 15:28:07 +0800	[thread overview]
Message-ID: <23818a08294a6b32aa9c8eaf0f444eaef60080b8.camel@icenowy.me> (raw)
In-Reply-To: <20220930073845.6309-1-hal.feng@linux.starfivetech.com>

在 2022-09-30星期五的 15:38 +0800,Hal Feng写道:
> From: Jianlong Huang <jianlong.huang@starfivetech.com>
> 
> Add pinctrl bindings for StarFive JH7110 SoC.
> 
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
> ---
>  .../pinctrl/starfive,jh7110-pinctrl.yaml      | 202
> ++++++++++++++++++
>  1 file changed, 202 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> 
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> new file mode 100644
> index 000000000000..482012ad8a14
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-
> pinctrl.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Pin Controller Device Tree Bindings
> +
> +description: |
> +  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
> +
> +maintainers:
> +  - Jianlong Huang <jianlong.huang@starfivetech.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +    - starfive,jh7110-sys-pinctrl
> +    - starfive,jh7110-aon-pinctrl
> +
> +  reg:
> +    minItems: 2
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: control
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  interrupts:
> +    maxItems: 1
> +    description: The GPIO parent interrupt.
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  ngpios:
> +    enum:
> +    - 64
> +    - 4
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - "#gpio-cells"
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +patternProperties:
> +  '-[0-9]+$':
> +    type: object
> +    patternProperties:
> +      '-pins$':
> +        type: object
> +        description: |
> +          A pinctrl node should contain at least one subnode
> representing the
> +          pinctrl groups available on the machine. Each subnode will
> list the
> +          pins it needs, and how they should be configured, with
> regard to
> +          muxer configuration, system signal configuration, pin
> groups for
> +          vin/vout module, pin voltage, mux functions for output,
> mux functions
> +          for output enable, mux functions for input.
> +
> +        properties:
> +          starfive,pins:
> +            description: |
> +              The list of pin identifiers that properties in the
> node apply to.
> +              This should be set using the PAD_GPIOX macros.
> +              This has to be specified.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 63

Hi,

I am adapting for Pine64's Star64 board, which utilizes a JH7110 SoC.

It does not features a USB overcurrent pin as GPIO, thus this pin needs
to be routed in PIO controller to fixed 1 (by writing 1 to
SYS_IOMUX_CFGSAIF__SYSCFG_FMUX_32[22:16]).

I think this kind of situation needs to be considered as part of DT
binding.

BTW if you have any difficulty refactoring the DT binding to standard
pinconf one, I am free to provide help.

Thanks,
Icenowy Zheng

> +
> +          starfive,pinmux:
> +            description: |
> +              The list of GPIOs and their mux functions that
> properties in the
> +              node apply to. This should be set using the
> PAD_GPIOX_FUNC_SEL
> +              macro with its value.
> +              This is optional for some pins.
> +              The value of PAD_GPIOX_FUNC_SEL macro can selects:
> +                0: GPIOX mux function 0,
> +                1: GPIOX mux function 1,
> +                2: GPIOX mux function 2.
> +
> +          starfive,pin-ioconfig:
> +            description: |
> +              This is used to configure the core settings of system
> signals.
> +              The combination of GPIO_IE or GPIO_DS or GPIO_PU or
> GPIO_PD or
> +              GPIO_SLEW or GPIO_SMT or GPIO_POS.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +
> +          starfive,padmux:
> +            description: |
> +              The padmux is for vin/vout module to select pin
> groups.
> +              0: vout will be set at pins from PAD_GPIO7 to
> PAD_GPIO34,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO6 to
> PAD_GPIO20.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              1: vout will be set at pins from PAD_GPIO36 to
> PAD_GPIO63,
> +                 when PAD_GPIOX_FUNC_SEL is set as 1.
> +                 vin will be set at pins from PAD_GPIO21 to
> PAD_GPIO35.
> +                 when PAD_GPIOX_FUNC_SEL is set as 2.
> +              2: vin will be set at pins from PAD_GPIO36 to
> PAD_GPIO50,
> +                 when PAD_GPIOX_FUNC_SEL is set as 2
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-syscon:
> +            description: |
> +              This is used to set pin voltage,
> +              0: 3.3V, 1: 2.5V, 2: 1.8V.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          starfive,pin-gpio-dout:
> +            description: |
> +              This is used to set their mux functions for output.
> +              This should be set using the GPO_XXX macro,
> +              such as GPO_LOW, GPO_UART0_SOUT.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 107
> +
> +          starfive,pin-gpio-doen:
> +            description: |
> +              This is used to set their mux functions for output
> enable.
> +              This should be set using the OEN_XXX macro,
> +              such as OEN_LOW, OEN_I2C0_IC_CLK_OE.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 49
> +
> +          starfive,pin-gpio-din:
> +            description: |
> +              This is used to set their mux functions for input.
> +              This should be set using the GPI_XXX macro,
> +              such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 90
> +
> +        additionalProperties: false
> +
> +    additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive-jh7110-sys.h>
> +    #include <dt-bindings/reset/starfive-jh7110.h>
> +    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +
> +    gpio: gpio@13040000 {
> +      compatible = "starfive,jh7110-sys-pinctrl";
> +      reg = <0x0 0x13040000 0x0 0x10000>;
> +      reg-names = "control";
> +      clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
> +      resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
> +      interrupts = <86>;
> +      interrupt-controller;
> +      #gpio-cells = <2>;
> +      ngpios = <64>;
> +      status = "okay";
> +
> +      uart0_pins: uart0-pins {
> +        uart0-pins-tx {
> +          starfive,pins = <PAD_GPIO5>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
> +          starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
> +          starfive,pin-gpio-doen = <OEN_LOW>;
> +        };
> +
> +        uart0-pins-rx {
> +          starfive,pins = <PAD_GPIO6>;
> +          starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
> +          starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
> +          starfive,pin-gpio-doen = <OEN_HIGH>;
> +          starfive,pin-gpio-din =  <GPI_UART0_SIN>;
> +        };
> +      };
> +    };
> +
> +    &uart0 {
> +      pinctrl-names = "default";
> +      pinctrl-0 = <&uart0_pins>;
> +      status = "okay";
> +    };
> +
> +...


  parent reply	other threads:[~2022-10-20  7:29 UTC|newest]

Thread overview: 105+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-29 14:31 [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Hal Feng
2022-09-29 14:31 ` [PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings Hal Feng
2022-09-29 14:34   ` Krzysztof Kozlowski
2022-10-08  3:44     ` Hal Feng
2022-09-29 14:31 ` [PATCH v1 02/30] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2022-09-29 14:34   ` Krzysztof Kozlowski
2022-09-29 14:31 ` [PATCH v1 03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2022-09-29 14:35   ` Krzysztof Kozlowski
2022-09-29 14:31 ` [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs Hal Feng
2022-09-29 14:36   ` Krzysztof Kozlowski
2022-09-29 15:33   ` Conor Dooley
2022-10-03  9:26     ` Ben Dooks
2022-10-08 18:54       ` Hal Feng
2022-09-29 14:32 ` [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver Hal Feng
2022-09-29 15:32   ` Conor Dooley
2022-09-29 17:57   ` Ben Dooks
2022-10-05 13:44     ` Emil Renner Berthing
2022-10-05 13:48       ` Ben Dooks
2022-10-05 13:55         ` Emil Renner Berthing
2022-10-05 14:05           ` Conor Dooley
2022-10-08 18:07             ` Hal Feng
2022-09-29 14:32 ` [PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support Hal Feng
2022-09-29 14:32 ` [PATCH v1 07/30] reset: starfive: jh7100: Use 32bit I/O on 32bit registers Hal Feng
2022-09-29 14:32 ` [PATCH v1 08/30] reset: starfive: jh7100: Use regmap APIs to operate registers Hal Feng
2022-09-29 14:32 ` [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree Hal Feng
2022-09-30 20:49   ` Rob Herring
2022-10-05 13:20     ` Emil Renner Berthing
2022-09-29 14:32 ` [PATCH v1 10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c' Hal Feng
2022-09-29 14:45 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Krzysztof Kozlowski
2022-09-29 17:59   ` Conor Dooley
2022-10-01  1:13     ` hal.feng
2022-09-29 16:35 ` [PATCH v1 11/30] dt-bindings: reset: Add StarFive JH7110 reset definitions Hal Feng
2022-09-29 17:51 ` [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings Hal Feng
2022-09-29 18:21   ` Rob Herring
2022-09-29 18:40     ` Rob Herring
2022-09-29 18:43   ` Rob Herring
2022-10-11 15:30     ` Hal Feng
2022-10-11 16:36       ` Krzysztof Kozlowski
2022-10-12 13:16         ` Hal Feng
2022-10-12 13:33           ` Krzysztof Kozlowski
2022-10-12 14:05             ` Conor Dooley
2022-10-12 15:21               ` Hal Feng
2022-10-12 14:53             ` Hal Feng
2022-10-12  8:01       ` Emil Renner Berthing
2022-09-29 17:53 ` [PATCH v1 13/30] reset: starfive: Add StarFive JH7110 SoC support Hal Feng
2022-09-29 17:54 ` [PATCH v1 14/30] clk: starfive: Factor out common clock driver code Hal Feng
2022-09-30 21:43   ` Stephen Boyd
2022-09-29 17:56 ` [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers Hal Feng
2022-09-30 21:48   ` Stephen Boyd
2022-10-05 13:14     ` Emil Renner Berthing
2022-10-12 23:05       ` Stephen Boyd
2022-10-23  4:11         ` Hal Feng
2022-10-23 10:25           ` Conor Dooley
2022-10-28  3:16             ` Hal Feng
2022-10-27  1:26           ` Stephen Boyd
2022-10-28  2:46             ` Hal Feng
2022-09-29 17:56 ` [PATCH v1 16/30] dt-bindings: clock: Add StarFive JH7110 system clock definitions Hal Feng
2022-09-29 22:26 ` [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings Hal Feng
2022-09-30  1:55   ` Rob Herring
2022-09-30 10:58   ` Krzysztof Kozlowski
2022-10-11 17:52     ` Hal Feng
2022-09-30  1:50 ` [PATCH v1 18/30] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2022-09-30  5:49 ` [PATCH v1 19/30] dt-bindings: clock: Add StarFive JH7110 always-on definitions Hal Feng
2022-09-30  5:56 ` [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings Hal Feng
2022-09-30 10:59   ` Krzysztof Kozlowski
2022-10-11 18:01     ` Hal Feng
2022-09-30 12:51   ` Rob Herring
2022-09-30  6:03 ` [PATCH v1 21/30] clk: starfive: Add StarFive JH7110 always-on clock driver Hal Feng
2022-09-30  6:08 ` [PATCH v1 22/30] pinctrl: Create subdirectory for StarFive drivers Hal Feng
2022-10-04  8:43   ` Linus Walleij
2022-09-30  6:14 ` [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" Hal Feng
2022-09-30 21:28   ` Rob Herring
2022-10-04  8:48     ` Linus Walleij
2022-10-04  8:58       ` Conor Dooley
2022-10-04  9:13         ` Linus Walleij
2022-10-04  9:21           ` Conor Dooley
2022-10-04  9:24             ` Conor Dooley
2022-10-06  9:07       ` Geert Uytterhoeven
2022-09-30  7:33 ` [PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Hal Feng
2022-09-30 11:00   ` Krzysztof Kozlowski
2022-09-30  7:38 ` [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings Hal Feng
2022-09-30 11:05   ` Krzysztof Kozlowski
2022-09-30 12:16   ` Rob Herring
2022-10-20  7:28   ` Icenowy Zheng [this message]
2022-09-30  7:43 ` [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver Hal Feng
2022-10-01 14:35   ` kernel test robot
2022-10-04  8:56   ` Linus Walleij
2022-10-05 13:31     ` Emil Renner Berthing
2022-10-14  2:05       ` Hal Feng
2022-09-30  7:49 ` [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree Hal Feng
2022-10-01 10:52   ` Conor Dooley
2022-10-03  7:45     ` Krzysztof Kozlowski
2022-10-14  9:41     ` Hal Feng
2022-09-30  7:53 ` [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board " Hal Feng
2022-10-01 11:14   ` Conor Dooley
2022-10-29  8:18     ` Hal Feng
2022-09-30  9:06 ` [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Hal Feng
2022-09-30 20:54   ` Ben Dooks
2022-09-30 21:41     ` Conor Dooley
2022-10-14  3:24       ` Hal Feng
2022-09-30 12:23 ` [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options Hal Feng
2022-09-30 12:37   ` Conor Dooley
2022-10-11 18:32     ` Hal Feng
2022-10-05 13:05 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Emil Renner Berthing
2022-10-08  3:18   ` Hal Feng

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