Re: Boot failure with 5.4-rc5, bisected to 0f0581b24bd0 ("spi: fsl: Convert to use CS GPIO descriptors")

[Christophe Leroy <christophe.leroy@c-s.fr>]

Le 27/11/2019 à 09:26, Linus Walleij a écrit :
> On Tue, Nov 26, 2019 at 8:14 PM Christophe Leroy
> <christophe.leroy@c-s.fr> wrote:
> 
>>> Digging a bit further, I see that devm_spi_register_master() fails in
>>> spi_register_controler() because ctlr->num_chipselect is 0
> 
> Aha, I see what the problem is I think. The old code for mpc8xxx had this:
> 
>         ngpios = of_gpio_count(np);
>         ngpios = max(ngpios, 0);
>         if (ngpios == 0 && !spisel_boot) {
>                 /*
>                  * SPI w/o chip-select line. One SPI device is still permitted
>                  * though.
>                  */
>                 pdata->max_chipselect = 1;
>                 return 0;
>         }
> (...)
>        master->num_chipselect = pdata->max_chipselect;
> 
> But the new code in the core has this:
> 
>      nb = gpiod_count(dev, "cs");
>      ctlr->num_chipselect = max_t(int, nb, ctlr->num_chipselect);
> 
> So it relied on inspecting the device tree and set  this to 1
> if it didn't find anything.
> 
> I will send a patch to test!
> 

I don't think that's the problem. In my device tree I have several gpios 
defined for the node:

spi: spi@a80 {
	#address-cells = <1>;
	#size-cells = <0>;
	cell-index = <0>;
	compatible = "fsl,spi", "fsl,cpm1-spi";
	reg = <0xa80 0x30 0x3d80 0x30>;
	interrupts = <5>;
	interrupt-parent = <&CPM_PIC>;
	mode = "cpu";
	gpios = <&CPM1_PIO_C 4 1	/* SICOFI 1 */
		 &CPM1_PIO_B 23 1	/* TEMP MCR */
		 &CPM1_PIO_C 8 1	/* SICOFI 2 */
		 &CPM1_PIO_C 12 1	/* EEPROM MIAE */
		 &CPM1_PIO_D 6 1	/* SICOFI 3 */
		 &CPM1_PIO_B 14 1	/* TEMP MPC885 */
		 &CPM1_PIO_B 21 1	/* EEPROM CMPC885 */
		 &FAV_CS_SPI 0 1	/* FAV SPI */
		 &FAV_CS_SPI 2 1>;	/* FAV POSTE FPGA */

	};

	sicofi@0 {
		compatible = "infineon,sicofi";
		spi-max-frequency = <1000000>;
		reg = <0>;
		spi-cs-high;
		spi-cpha;
	};

	lm74@1 {
		compatible = "ns,lm74";
		spi-max-frequency = <1000000>;
		reg = <1>;
		spi-cs-high;
	};

	sicofi@2 {
		compatible = "infineon,sicofi";
		spi-max-frequency = <1000000>;
		reg = <2>;
		spi-cs-high;
		spi-cpha;
	};

	eeprom@3 {
		compatible = "atmel,at25";
		spi-max-frequency = <1000000>;
		reg = <3>;
		spi-cs-high;
		at25,byte-len = <1024>;
		at25,addr-mode = <2>;
		at25,page-size = <32>;
	};

	sicofi@4 {
		compatible = "infineon,sicofi";
		spi-max-frequency = <1000000>;
		reg = <4>;
		spi-cs-high;
		spi-cpha;
	};

	lm74@5 {
		compatible = "ns,lm74";
		spi-max-frequency = <1000000>;
		reg = <5>;
		spi-cs-high;
	};

	eeprom@6 {
		compatible = "atmel,at25";
		spi-max-frequency = <1000000>;
		reg = <6>;
		spi-cs-high;
		at25,byte-len = <1024>;
		at25,addr-mode = <2>;
		at25,page-size = <32>;
	};

	iio: csfav@7 {
		compatible = "iio,ad7923";
		spi-max-frequency = <1000000>;
		reg = <7>;
		spi-cs-high;
		spi-cpol;
		#io-channel-cells = <1>;
	};

	csfavfpga@8 {
		compatible = "cs,fpga-poste";
		spi-max-frequency = <1000000>;
		reg = <8>;
		spi-cs-high;
	};
};

Christophe