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* [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions
       [not found] <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com>
@ 2020-06-05 20:23 ` Sergei Shtylyov
  2020-06-08 12:58   ` Geert Uytterhoeven
  2020-06-18 19:46 ` [PATCH] pinctrl: sh-pfc: r8a77970: " Sergei Shtylyov
  2020-06-19 17:54 ` Sergei Shtylyov
  2 siblings, 1 reply; 6+ messages in thread
From: Sergei Shtylyov @ 2020-06-05 20:23 UTC (permalink / raw)
  To: Linus Walleij, Geert Uytterhoeven, linux-gpio, linux-renesas-soc

Add the RPC pins/groups/functions to the R8A77980 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.

Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo.

 drivers/pinctrl/sh-pfc/pfc-r8a77980.c |   76 ++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

Index: renesas-devel/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
===================================================================
--- renesas-devel.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ renesas-devel/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -1710,6 +1710,64 @@ static const unsigned int qspi1_data4_mu
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
 };
 
+/* - RPC -------------------------------------------------------------------- */
+static const unsigned int rpc_clk1_pins[] = {
+	/* Octal-SPI flash: C/SCLK */
+	RCAR_GP_PIN(5, 0),
+};
+static const unsigned int rpc_clk1_mux[] = {
+	QSPI0_SPCLK_MARK,
+};
+static const unsigned int rpc_clk2_pins[] = {
+	/* HyperFlash: CK, CK# */
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int rpc_clk2_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
+};
+static const unsigned int rpc_ctrl_pins[] = {
+	/* Octal-SPI flash: S#/CS, DQS */
+	/* HyperFlash: CS#, RDS */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+	/* DQ[0:7] */
+	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int rpc_data_mux[] = {
+	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+static const unsigned int rpc_reset_pins[] = {
+	/* RPC_RESET# */
+	RCAR_GP_PIN(5, 12),
+};
+static const unsigned int rpc_reset_mux[] = {
+	RPC_RESET_N_MARK,
+};
+static const unsigned int rpc_int_pins[] = {
+	/* RPC_INT# */
+	RCAR_GP_PIN(5, 14),
+};
+static const unsigned int rpc_int_mux[] = {
+	RPC_INT_N_MARK,
+};
+static const unsigned int rpc_wp_pins[] = {
+	/* RPC_WP# */
+	RCAR_GP_PIN(5, 13),
+};
+static const unsigned int rpc_wp_mux[] = {
+	RPC_WP_N_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -2126,6 +2184,13 @@ static const struct sh_pfc_pin_group pin
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
 	SH_PFC_PIN_GROUP(qspi1_data2),
 	SH_PFC_PIN_GROUP(qspi1_data4),
+	SH_PFC_PIN_GROUP(rpc_clk1),
+	SH_PFC_PIN_GROUP(rpc_clk2),
+	SH_PFC_PIN_GROUP(rpc_ctrl),
+	SH_PFC_PIN_GROUP(rpc_data),
+	SH_PFC_PIN_GROUP(rpc_reset),
+	SH_PFC_PIN_GROUP(rpc_int),
+	SH_PFC_PIN_GROUP(rpc_wp),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2362,6 +2427,16 @@ static const char * const qspi1_groups[]
 	"qspi1_data4",
 };
 
+static const char * const rpc_groups[] = {
+	"rpc_clk1",
+	"rpc_clk2",
+	"rpc_ctrl",
+	"rpc_data",
+	"rpc_reset",
+	"rpc_int",
+	"rpc_wp",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -2460,6 +2535,7 @@ static const struct sh_pfc_function pinm
 	SH_PFC_FUNCTION(pwm4),
 	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(qspi1),
+	SH_PFC_FUNCTION(rpc),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions
  2020-06-05 20:23 ` [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions Sergei Shtylyov
@ 2020-06-08 12:58   ` Geert Uytterhoeven
  0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2020-06-08 12:58 UTC (permalink / raw)
  To: Sergei Shtylyov; +Cc: Linus Walleij, open list:GPIO SUBSYSTEM, Linux-Renesas

On Fri, Jun 5, 2020 at 10:23 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the RPC pins/groups/functions to the R8A77980 PFC driver.
> They can be used if an Octal-SPI flash or HyperFlash is connected.
>
> Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v5.9.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] pinctrl: sh-pfc: r8a77970: add RPC pins, groups, and functions
       [not found] <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com>
  2020-06-05 20:23 ` [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions Sergei Shtylyov
@ 2020-06-18 19:46 ` Sergei Shtylyov
  2020-06-19 12:58   ` Geert Uytterhoeven
  2020-06-19 17:54 ` Sergei Shtylyov
  2 siblings, 1 reply; 6+ messages in thread
From: Sergei Shtylyov @ 2020-06-18 19:46 UTC (permalink / raw)
  To: Linus Walleij, Geert Uytterhoeven, linux-gpio, linux-renesas-soc

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: pinctrl: sh-pfc: r8a77970: Add RPC pins, groups, and functions

Add the RPC pins/groups/functions to the R8A77970 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.

Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo.

 drivers/pinctrl/sh-pfc/pfc-r8a77970.c |   76 ++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
===================================================================
--- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
 };
 
+/* - RPC -------------------------------------------------------------------- */
+static const unsigned int rpc_clk1_pins[] = {
+	/* Octal-SPI flash: C/SCLK */
+	RCAR_GP_PIN(5, 0),
+};
+static const unsigned int rpc_clk1_mux[] = {
+	QSPI0_SPCLK_MARK,
+};
+static const unsigned int rpc_clk2_pins[] = {
+	/* HyperFlash: CK, CK# */
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int rpc_clk2_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
+};
+static const unsigned int rpc_ctrl_pins[] = {
+	/* Octal-SPI flash: S#/CS, DQS */
+	/* HyperFlash: CS#, RDS */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+	/* DQ[0:7] */
+	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int rpc_data_mux[] = {
+	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+static const unsigned int rpc_reset_pins[] = {
+	/* RPC_RESET# */
+	RCAR_GP_PIN(5, 12),
+};
+static const unsigned int rpc_reset_mux[] = {
+	RPC_RESET_N_MARK,
+};
+static const unsigned int rpc_int_pins[] = {
+	/* RPC_INT# */
+	RCAR_GP_PIN(5, 14),
+};
+static const unsigned int rpc_int_mux[] = {
+	RPC_INT_N_MARK,
+};
+static const unsigned int rpc_wp_pins[] = {
+	/* RPC_WP# */
+	RCAR_GP_PIN(5, 13),
+};
+static const unsigned int rpc_wp_mux[] = {
+	RPC_WP_N_MARK,
+};
+
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
@@ -1750,6 +1808,13 @@ static const struct sh_pfc_pin_group pin
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
 	SH_PFC_PIN_GROUP(qspi1_data2),
 	SH_PFC_PIN_GROUP(qspi1_data4),
+	SH_PFC_PIN_GROUP(rpc_clk1),
+	SH_PFC_PIN_GROUP(rpc_clk2),
+	SH_PFC_PIN_GROUP(rpc_ctrl),
+	SH_PFC_PIN_GROUP(rpc_data),
+	SH_PFC_PIN_GROUP(rpc_reset),
+	SH_PFC_PIN_GROUP(rpc_int),
+	SH_PFC_PIN_GROUP(rpc_wp),
 	SH_PFC_PIN_GROUP(scif_clk_a),
 	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(scif0_data),
@@ -1954,6 +2019,16 @@ static const char * const qspi1_groups[]
 	"qspi1_data4",
 };
 
+static const char * const rpc_groups[] = {
+	"rpc_clk1",
+	"rpc_clk2",
+	"rpc_ctrl",
+	"rpc_data",
+	"rpc_reset",
+	"rpc_int",
+	"rpc_wp",
+};
+
 static const char * const scif_clk_groups[] = {
 	"scif_clk_a",
 	"scif_clk_b",
@@ -2039,6 +2114,7 @@ static const struct sh_pfc_function pinm
 	SH_PFC_FUNCTION(pwm4),
 	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(qspi1),
+	SH_PFC_FUNCTION(rpc),
 	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] pinctrl: sh-pfc: r8a77970: add RPC pins, groups, and functions
  2020-06-18 19:46 ` [PATCH] pinctrl: sh-pfc: r8a77970: " Sergei Shtylyov
@ 2020-06-19 12:58   ` Geert Uytterhoeven
  2020-06-19 15:23     ` Sergei Shtylyov
  0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2020-06-19 12:58 UTC (permalink / raw)
  To: Sergei Shtylyov; +Cc: Linus Walleij, linux-gpio, Linux-Renesas

Hi Sergei,

On Thu, Jun 18, 2020 at 9:46 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Subject: pinctrl: sh-pfc: r8a77970: Add RPC pins, groups, and functions
>
> Add the RPC pins/groups/functions to the R8A77970 PFC driver.
> They can be used if an Octal-SPI flash or HyperFlash is connected.
>
> Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks for your patch!

> --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
> +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
> @@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu
>         QSPI1_IO2_MARK, QSPI1_IO3_MARK
>  };
>
> +/* - RPC -------------------------------------------------------------------- */
> +static const unsigned int rpc_clk1_pins[] = {
> +       /* Octal-SPI flash: C/SCLK */
> +       RCAR_GP_PIN(5, 0),
> +};
> +static const unsigned int rpc_clk1_mux[] = {
> +       QSPI0_SPCLK_MARK,
> +};
> +static const unsigned int rpc_clk2_pins[] = {
> +       /* HyperFlash: CK, CK# */
> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
> +};
> +static const unsigned int rpc_clk2_mux[] = {
> +       QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
> +};
> +static const unsigned int rpc_ctrl_pins[] = {
> +       /* Octal-SPI flash: S#/CS, DQS */
> +       /* HyperFlash: CS#, RDS */
> +       RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
> +};
> +static const unsigned int rpc_ctrl_mux[] = {
> +       QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,

Shouldn't the above read

    QSPI0_SSL_MARK, QSPI1_SSL_MARK,

?

I seem to have overlooked the same issue in commit aa2165cf2ece9176
("pinctrl: sh-pfc: r8a77980: Add RPC pins, groups, and functions") in
sh-pfc-for-v5.9, which I can fix myself.

With the above sorted out:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
and will queue in sh-pfc-for-v5.9 after fixing.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] pinctrl: sh-pfc: r8a77970: add RPC pins, groups, and functions
  2020-06-19 12:58   ` Geert Uytterhoeven
@ 2020-06-19 15:23     ` Sergei Shtylyov
  0 siblings, 0 replies; 6+ messages in thread
From: Sergei Shtylyov @ 2020-06-19 15:23 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-gpio, Linux-Renesas

On 06/19/2020 03:58 PM, Geert Uytterhoeven wrote:

>> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> Subject: pinctrl: sh-pfc: r8a77970: Add RPC pins, groups, and functions
>>
>> Add the RPC pins/groups/functions to the R8A77970 PFC driver.
>> They can be used if an Octal-SPI flash or HyperFlash is connected.
>>
>> Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> Thanks for your patch!
> 
>> --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
>> +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
>> @@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu
>>         QSPI1_IO2_MARK, QSPI1_IO3_MARK
>>  };
>>
>> +/* - RPC -------------------------------------------------------------------- */
>> +static const unsigned int rpc_clk1_pins[] = {
>> +       /* Octal-SPI flash: C/SCLK */
>> +       RCAR_GP_PIN(5, 0),
>> +};
>> +static const unsigned int rpc_clk1_mux[] = {
>> +       QSPI0_SPCLK_MARK,
>> +};
>> +static const unsigned int rpc_clk2_pins[] = {
>> +       /* HyperFlash: CK, CK# */
>> +       RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
>> +};
>> +static const unsigned int rpc_clk2_mux[] = {
>> +       QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
>> +};
>> +static const unsigned int rpc_ctrl_pins[] = {
>> +       /* Octal-SPI flash: S#/CS, DQS */
>> +       /* HyperFlash: CS#, RDS */
>> +       RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
>> +};
>> +static const unsigned int rpc_ctrl_mux[] = {
>> +       QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
> 
> Shouldn't the above read
> 
>     QSPI0_SSL_MARK, QSPI1_SSL_MARK,
> 
> ?

   Indeed! Stupid copy&paste error... :-(
> I seem to have overlooked the same issue in commit aa2165cf2ece9176
> ("pinctrl: sh-pfc: r8a77980: Add RPC pins, groups, and functions") in
> sh-pfc-for-v5.9, which I can fix myself.
> 
> With the above sorted out:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> and will queue in sh-pfc-for-v5.9 after fixing.

   So I do need to repost? OK...

> Gr{oetje,eeting}s,
> 
>                         Geert

MBR, Sergei


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] pinctrl: sh-pfc: r8a77970: add RPC pins, groups, and functions
       [not found] <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com>
  2020-06-05 20:23 ` [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions Sergei Shtylyov
  2020-06-18 19:46 ` [PATCH] pinctrl: sh-pfc: r8a77970: " Sergei Shtylyov
@ 2020-06-19 17:54 ` Sergei Shtylyov
  2 siblings, 0 replies; 6+ messages in thread
From: Sergei Shtylyov @ 2020-06-19 17:54 UTC (permalink / raw)
  To: Linus Walleij, Geert Uytterhoeven, linux-gpio, linux-renesas-soc

Add the RPC pins/groups/functions to the R8A77970 PFC driver.
They can be used if an Octal-SPI flash or HyperFlash is connected.

Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo.

Changes in version 2:
- fixed up the initializer for rpc_ctrl_mux[];
- added Geert's tag.

 drivers/pinctrl/sh-pfc/pfc-r8a77970.c |   76 ++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
===================================================================
--- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu
 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
 };
 
+/* - RPC -------------------------------------------------------------------- */
+static const unsigned int rpc_clk1_pins[] = {
+	/* Octal-SPI flash: C/SCLK */
+	RCAR_GP_PIN(5, 0),
+};
+static const unsigned int rpc_clk1_mux[] = {
+	QSPI0_SPCLK_MARK,
+};
+static const unsigned int rpc_clk2_pins[] = {
+	/* HyperFlash: CK, CK# */
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int rpc_clk2_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
+};
+static const unsigned int rpc_ctrl_pins[] = {
+	/* Octal-SPI flash: S#/CS, DQS */
+	/* HyperFlash: CS#, RDS */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int rpc_ctrl_mux[] = {
+	QSPI0_SSL_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int rpc_data_pins[] = {
+	/* DQ[0:7] */
+	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int rpc_data_mux[] = {
+	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+static const unsigned int rpc_reset_pins[] = {
+	/* RPC_RESET# */
+	RCAR_GP_PIN(5, 12),
+};
+static const unsigned int rpc_reset_mux[] = {
+	RPC_RESET_N_MARK,
+};
+static const unsigned int rpc_int_pins[] = {
+	/* RPC_INT# */
+	RCAR_GP_PIN(5, 14),
+};
+static const unsigned int rpc_int_mux[] = {
+	RPC_INT_N_MARK,
+};
+static const unsigned int rpc_wp_pins[] = {
+	/* RPC_WP# */
+	RCAR_GP_PIN(5, 13),
+};
+static const unsigned int rpc_wp_mux[] = {
+	RPC_WP_N_MARK,
+};
+
 /* - SCIF Clock ------------------------------------------------------------- */
 static const unsigned int scif_clk_a_pins[] = {
 	/* SCIF_CLK */
@@ -1750,6 +1808,13 @@ static const struct sh_pfc_pin_group pin
 	SH_PFC_PIN_GROUP(qspi1_ctrl),
 	SH_PFC_PIN_GROUP(qspi1_data2),
 	SH_PFC_PIN_GROUP(qspi1_data4),
+	SH_PFC_PIN_GROUP(rpc_clk1),
+	SH_PFC_PIN_GROUP(rpc_clk2),
+	SH_PFC_PIN_GROUP(rpc_ctrl),
+	SH_PFC_PIN_GROUP(rpc_data),
+	SH_PFC_PIN_GROUP(rpc_reset),
+	SH_PFC_PIN_GROUP(rpc_int),
+	SH_PFC_PIN_GROUP(rpc_wp),
 	SH_PFC_PIN_GROUP(scif_clk_a),
 	SH_PFC_PIN_GROUP(scif_clk_b),
 	SH_PFC_PIN_GROUP(scif0_data),
@@ -1954,6 +2019,16 @@ static const char * const qspi1_groups[]
 	"qspi1_data4",
 };
 
+static const char * const rpc_groups[] = {
+	"rpc_clk1",
+	"rpc_clk2",
+	"rpc_ctrl",
+	"rpc_data",
+	"rpc_reset",
+	"rpc_int",
+	"rpc_wp",
+};
+
 static const char * const scif_clk_groups[] = {
 	"scif_clk_a",
 	"scif_clk_b",
@@ -2039,6 +2114,7 @@ static const struct sh_pfc_function pinm
 	SH_PFC_FUNCTION(pwm4),
 	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(qspi1),
+	SH_PFC_FUNCTION(rpc),
 	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-19 17:54 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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     [not found] <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com>
2020-06-05 20:23 ` [PATCH] pinctrl: sh-pfc: r8a77980: add RPC pins, groups, and functions Sergei Shtylyov
2020-06-08 12:58   ` Geert Uytterhoeven
2020-06-18 19:46 ` [PATCH] pinctrl: sh-pfc: r8a77970: " Sergei Shtylyov
2020-06-19 12:58   ` Geert Uytterhoeven
2020-06-19 15:23     ` Sergei Shtylyov
2020-06-19 17:54 ` Sergei Shtylyov

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