From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53C23C433FE for ; Fri, 7 Oct 2022 19:39:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229853AbiJGTjW (ORCPT ); Fri, 7 Oct 2022 15:39:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbiJGTjD (ORCPT ); Fri, 7 Oct 2022 15:39:03 -0400 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [IPv6:2001:4b7a:2000:18::170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC89510C4E9; Fri, 7 Oct 2022 12:38:59 -0700 (PDT) Received: from [192.168.1.101] (95.49.30.201.neoplus.adsl.tpnet.pl [95.49.30.201]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 4D443200A6; Fri, 7 Oct 2022 21:38:57 +0200 (CEST) Message-ID: <5c2732c7-3411-e4ff-5df0-5bfa080092c9@somainline.org> Date: Fri, 7 Oct 2022 21:38:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 1/4] arm64: dts: qcom: sdm630: add UART pin functions Content-Language: en-US To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221006104104.171368-1-krzysztof.kozlowski@linaro.org> From: Konrad Dybcio In-Reply-To: <20221006104104.171368-1-krzysztof.kozlowski@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 6.10.2022 12:41, Krzysztof Kozlowski wrote: > Configure UART1 and UART2 pins to respective functions in default state, > otherwise the pins might stay as GPIOs. > > Signed-off-by: Krzysztof Kozlowski > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi > index e119060ac56c..bc7c341e793c 100644 > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi > @@ -723,6 +723,7 @@ tlmm: pinctrl@3100000 { > > blsp1_uart1_default: blsp1-uart1-default { > pins = "gpio0", "gpio1", "gpio2", "gpio3"; > + function = "blsp_uart1"; > drive-strength = <2>; > bias-disable; > }; > @@ -735,6 +736,7 @@ blsp1_uart1_sleep: blsp1-uart1-sleep { > > blsp1_uart2_default: blsp1-uart2-default { > pins = "gpio4", "gpio5"; > + function = "blsp_uart2"; > drive-strength = <2>; > bias-disable; > };