Re: [PATCH 1/1] pinctrl: amd: disable and mask interrupts on probe

From: Basavaraj Natikar <bnatikar@amd.com>
To: Sachi King <nakato@nakato.io>,
	linux-gpio@vger.kernel.org, basavaraj.natikar@amd.com
Cc: linux-kernel@vger.kernel.org, "Limonciello,
	Mario" <mario.limonciello@amd.com>,
	Shyam-sundar S-k <Shyam-sundar.S-k@amd.com>,
	"Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@amd.com>
Subject: Re: [PATCH 1/1] pinctrl: amd: disable and mask interrupts on probe
Date: Sat, 9 Oct 2021 01:27:16 +0530	[thread overview]
Message-ID: <5d683882-257d-87b2-20aa-0871e2902090@amd.com> (raw)
In-Reply-To: <20211001161714.2053597-2-nakato@nakato.io>

On 10/1/2021 9:47 PM, Sachi King wrote:
> [CAUTION: External Email]
>
> Some systems such as the Microsoft Surface Laptop 4 leave interrupts
> enabled and configured for use in sleep states on boot, which cause
> unexpected behaviour such as spurious wakes and failed resumes in
> s2idle states.
>
> As interrupts should not be enabled until they are claimed and
> explicitly enabled, disabling any interrupts mistakenly left enabled by
> firmware should be safe.
>
> Signed-off-by: Sachi King <nakato@nakato.io>
> ---
>  drivers/pinctrl/pinctrl-amd.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index c001f2ed20f8..aa4136cd312d 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -830,6 +830,32 @@ static const struct pinconf_ops amd_pinconf_ops = {
>         .pin_config_group_set = amd_pinconf_group_set,
>  };
>
> +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) {
> +       struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
> +       unsigned long flags;
> +       u32 pin_reg, mask;
> +       int i;
> +
> +       mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3)
> +               | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF)
> +               | BIT(INTERRUPT_MASK_OFF) | BIT(WAKE_CNTRL_OFF_S4);

Could you please correct INTERRUPT_MASK_OFF , added twice.

Thanks,
Basavaraj 

> +
> +       for (i = 0; i < desc->npins; i++) {
> +               int pin = desc->pins[i].number;
> +               const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
> +               if (!pd)
> +                       continue;
> +
> +               raw_spin_lock_irqsave(&gpio_dev->lock, flags);
> +
> +               pin_reg = readl(gpio_dev->base + i * 4);
> +               pin_reg &= ~mask;
> +               writel(pin_reg, gpio_dev->base + i * 4);
> +
> +               raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
> +       }
> +}
> +
>  #ifdef CONFIG_PM_SLEEP
>  static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
>  {
> @@ -967,6 +993,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
>                 return PTR_ERR(gpio_dev->pctrl);
>         }
>
> +       /* Disable and mask interrupts */
> +       amd_gpio_irq_init(gpio_dev);
> +
>         girq = &gpio_dev->gc.irq;
>         girq->chip = &amd_gpio_irqchip;
>         /* This will let us handle the parent IRQ in the driver */
> --
> 2.33.0
>