From: Linus Walleij <linus.walleij@linaro.org>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-sunxi <linux-sunxi@googlegroups.com>,
Maxime Ripard <maxime.ripard@bootlin.com>
Subject: Re: [PATCH v5 1/6] pinctrl: sunxi: v3s: introduce support for V3
Date: Mon, 5 Aug 2019 12:36:03 +0200 [thread overview]
Message-ID: <CACRpkdY65Ob-zbd+c4reUzYtXdk441horQ0ykL08YeBrgXWqQw@mail.gmail.com> (raw)
In-Reply-To: <20190728031227.49140-2-icenowy@aosc.io>
On Sun, Jul 28, 2019 at 5:13 AM Icenowy Zheng <icenowy@aosc.io> wrote:
> Introduce the GPIO pins that is only available on V3 (not on V3s) to the
> V3s pinctrl driver.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Patch applied to the pinctrl tree.
Ypurs,
Linus Walleij
next prev parent reply other threads:[~2019-08-05 10:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-28 3:12 [PATCH v5 0/6] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-28 3:12 ` [PATCH v5 1/6] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-08-05 10:36 ` Linus Walleij [this message]
2019-07-28 3:12 ` [PATCH v5 2/6] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
2019-07-28 3:12 ` [PATCH v5 3/6] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-28 3:12 ` [PATCH v5 4/6] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-28 3:12 ` [PATCH v5 5/6] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-28 3:12 ` [PATCH v5 6/6] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-08-12 8:07 ` [PATCH v5 0/6] Support for Allwinner V3/S3L and Sochip S3 Maxime Ripard
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