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From: Linus Walleij <linus.walleij@linaro.org>
To: Qianggui Song <qianggui.song@amlogic.com>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Carlo Caione <carlo@caione.org>, Rob Herring <robh+dt@kernel.org>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	Hanjie Lin <hanjie.lin@amlogic.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Amlogic Meson..."
	<linux-amlogic@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 2/3] pinctrl: meson: add pinctrl driver support for Meson-A1 SoC
Date: Tue, 19 Nov 2019 15:56:14 +0100	[thread overview]
Message-ID: <CACRpkdbQ08ivkyVnuy_+=YqHXcXQDUY8aOpp6evdGLofe3FM0g@mail.gmail.com> (raw)
In-Reply-To: <1573819429-6937-3-git-send-email-qianggui.song@amlogic.com>

On Fri, Nov 15, 2019 at 1:03 PM Qianggui Song <qianggui.song@amlogic.com> wrote:

> Meson A1 SoC share the same register layout of pinmux with previous
> Meson-G12A, however there is difference for gpio and pin config register
> in A1. The main difference is that registers before A1 are grouped by
> function while those of A1 are by bank. The new register layout is as
> below:
>
> /* first bank */              /* addr */
> - P_PADCTRL_GPIOP_I         base + 0x00 << 2
> - P_PADCTRL_GPIOP_O         base + 0x01 << 2
> - P_PADCTRL_GPIOP_OEN       base + 0x02 << 2
> - P_PADCTRL_GPIOP_PULL_EN   base + 0x03 << 2
> - P_PADCTRL_GPIOP_PULL_UP   base + 0x04 << 2
> - P_PADCTRL_GPIOP_DS        base + 0x05 << 2
>
> /* second bank */
> - P_PADCTRL_GPIOB_I         base + 0x10 << 2
> - P_PADCTRL_GPIOB_O         base + 0x11 << 2
> - P_PADCTRL_GPIOB_OEN       base + 0x12 << 2
> - P_PADCTRL_GPIOB_PULL_EN   base + 0x13 << 2
> - P_PADCTRL_GPIOB_PULL_UP   base + 0x14 << 2
> - P_PADCTRL_GPIOB_DS        base + 0x15 << 2
>
> Each bank contains at least 6 registers to be configured, if one bank
> has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
> Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
> is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
> ,0x25 according to above register layout. For previous chips, registers
> are grouped according to their functions while registers of A1 are
> according to bank.Also note that there is no AO bank any more in A1.
>
> Current Meson pinctrl driver can cover such change by using base address
> of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
> make wrong value to reg_ds for Socs that do not support drive-strength
> like AXG.To make things simple, add an extra dt parser function for
> a1 and remain the old dt parser function for only reg parsing.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>

Patch applied with Neil's Review tag.

Yours,
Linus Walleij

  parent reply	other threads:[~2019-11-19 14:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 12:03 [PATCH v6 0/3] pinctrl: meson-a1: add pinctrl driver Qianggui Song
2019-11-15 12:03 ` [PATCH v6 1/3] pinctrl: meson: add a new callback for SoCs fixup Qianggui Song
2019-11-15 12:51   ` Neil Armstrong
2019-11-19 14:54   ` Linus Walleij
2019-11-15 12:03 ` [PATCH v6 2/3] pinctrl: meson: add pinctrl driver support for Meson-A1 SoC Qianggui Song
2019-11-15 12:52   ` Neil Armstrong
2019-11-19 14:56   ` Linus Walleij [this message]
2019-11-15 12:03 ` [PATCH v6 3/3] arm64: dts: meson: a1: add pinctrl controller support Qianggui Song
2019-11-15 12:53   ` Neil Armstrong
2019-12-09 22:13     ` Kevin Hilman

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