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[209.85.217.43]) by smtp.gmail.com with ESMTPSA id q10-20020a9f378a000000b006904fa86e7csm3684602uaq.2.2023.03.27.14.51.16 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Mar 2023 14:51:16 -0700 (PDT) Received: by mail-vs1-f43.google.com with SMTP id cz11so8785694vsb.6 for ; Mon, 27 Mar 2023 14:51:16 -0700 (PDT) X-Received: by 2002:a05:6102:4711:b0:425:f1e7:fecf with SMTP id ei17-20020a056102471100b00425f1e7fecfmr6513084vsb.7.1679953876235; Mon, 27 Mar 2023 14:51:16 -0700 (PDT) MIME-Version: 1.0 References: <20230323173019.3706069-1-dianders@chromium.org> In-Reply-To: From: Doug Anderson Date: Mon, 27 Mar 2023 14:51:04 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 00/14] Control Quad SPI pinctrl better on Qualcomm Chromebooks To: Linus Walleij Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Andy Gross , Rajendra Nayak , Rajesh Patil , Roja Rani Yarubandi , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi, On Mon, Mar 27, 2023 at 2:45=E2=80=AFPM Linus Walleij wrote: > > On Thu, Mar 23, 2023 at 6:31=E2=80=AFPM Douglas Anderson wrote: > > > The main goal of this series is to do a better job of cI can apply ontr= oling the > > pins related to the "Quad SPI" IP block on Qualcomm Chromebooks. This > > is essentially 'v2' of my previous attempt in the patch ("arm64: dts: > > qcom: sc7180: Fix trogdor qspi pull direction") [1] but since it's > > spiraled out a bit and there are no patches that are exactly the same > > I've reset to v1. > > > > The early patches in this series are just no-op cleanup patches that > > can be applied. They're not terribly critical but since they are > > "Fixes" I've listed them first. > > > > The next patch in the series is a very simple and (hopefully) > > non-controversial SPI patch. It can be applied independently if > > anything else. > > > > Next, we have a bunch of pinctrl patches (including the device tree > > bindings related to them). I dunno what folks are going to think about > > these. If everyone hates them, we can drop them and just change the > > later patches in the series to use "input-enable" instead of > > "output-disable". It feels ugly to me, but it maybe less upheval. > > > > Next I removed the now-deprecated "input-enable" property from all > > Chromebooks. None of them were necessary. > > > > Finally, I did what I really wanted to do in the first place: attempt > > to cleanup the pinctrl states of the Quad SPI. These patches have a > > hard requirement on the pinctrl change. > > This looks good to me (TM) > > Do you have a merge plan? > I can queue the pinctrl patch into the pinctrl tree, and > the pinctrl binding patches. > > Will you take the rest to the SPI and SoC tree? > > Acked-by: Linus Walleij My thoughts: 1. Mark could land the SPI patch at any time, assuming he's OK with it. It can land totally independently. 2. First 7 dts patches could land in the Qualcomm tree. There are no dependencies on these ones other than the commit message of some of the later dts patches talking about the pinctrl patches. ...then... Option A: 3. You land the pinctrl and binding patches in an immutable branch and merge into pinctrl. 4. Bjorn merges the immutable branch into the Qulacomm tree and places the last 3 dts patches atop. Option B: 3. You Ack the pinctrl patches and Bjorn lands them all, plus the last 3 dts patches. Option C: 3. You land the pinctrl patches, then we want a few months and land the last 3 dts patches.