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References: <20221009181338.2896660-1-lis8215@gmail.com> <20221009181338.2896660-8-lis8215@gmail.com>
 <Y0R+q7BdxtFqeiT1@kroah.com>
In-Reply-To: <Y0R+q7BdxtFqeiT1@kroah.com>
From:   Siarhei Volkau <lis8215@gmail.com>
Date:   Tue, 11 Oct 2022 21:38:03 +0300
Message-ID: <CAKNVLfaNJjdVCeVCrOOw5xjsJ=gzJ2uFxAjgMA9tWHE=qFEECA@mail.gmail.com>
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the
 JZ4750/JZ4755 SoCs
To:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Vinod Koul <vkoul@kernel.org>,
        Paul Cercueil <paul@crapouillou.net>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        Jiri Slaby <jirislaby@kernel.org>, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        dmaengine@vger.kernel.org, linux-serial@vger.kernel.org,
        linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org
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=D0=BF=D0=BD, 10 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 23:20, Greg Kroah-=
Hartman <gregkh@linuxfoundation.org>:
> What does "clkdiv" mean here?

That means a clock divisor between the input oscillator and UART
peripheral clock source. Most Ingenic SoCs don't have that divisor,
so 1 is always in effect for them.
However, the JZ4750 and JZ4755 have switchable /2 clock divisor.

> If you only have 1 or 2 as an option

Yes, it is.

> just have 2 functions instead please.

Got it, will do that.

Thank you.