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Thu, 7 Jan 2021 02:52:45 -0800 Envelope-to: git@xilinx.com, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, syednwaris@gmail.com, vilhelm.gray@gmail.com, hancock@sedsystems.ca, bgolaszewski@baylibre.com, linus.walleij@linaro.org Received: from [172.30.17.109] (port=48692) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kxSuK-0004s4-OB; Thu, 07 Jan 2021 02:52:44 -0800 Subject: Re: [PATCH V4 5/5] gpio: gpio-xilinx: Add check if width exceeds 32 To: Linus Walleij , Michal Simek CC: Srinivas Neeli , Bartosz Golaszewski , Shubhrajyoti Datta , , Robert Hancock , William Breathitt Gray , Syed Nayyar Waris , "open list:GPIO SUBSYSTEM" , Linux ARM , "linux-kernel@vger.kernel.org" , References: <1609936000-28378-1-git-send-email-srinivas.neeli@xilinx.com> <1609936000-28378-6-git-send-email-srinivas.neeli@xilinx.com> <11abb0f7-407a-3509-ad50-cc7698147ee5@xilinx.com> From: Michal Simek Message-ID: Date: Thu, 7 Jan 2021 11:52:40 +0100 User-Agent: Mozilla/5.0 (X11; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2021 10:52:50.8195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c6c37ed-ef39-442f-6ca9-08d8b2fa60de X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT064.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4650 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 07. 01. 21 11:47, Linus Walleij wrote: > On Thu, Jan 7, 2021 at 11:29 AM Michal Simek wrote: >> On 07. 01. 21 11:17, Linus Walleij wrote: >>> On Wed, Jan 6, 2021 at 1:27 PM Srinivas Neeli wrote: > >>>> @@ -591,6 +591,9 @@ static int xgpio_probe(struct platform_device *pdev) >>>> if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) >>>> chip->gpio_width[0] = 32; >>> >>> This xlnx,gpio-width seems very much like the standard ngpios property >>> from Documentation/devicetree/bindings/gpio/gpio.txt >>> but I guess not much to do about that now. :/ >>> >>> Do you think you can add support for both? >> >> support for both is definitely possible but we need to handle also gpio >> width for second channel referenced by xlnx,gpio2-widht now. >> >> It means we could end up in situation which can be misleading for users >> where ngpios will be 10 and xlnx,gpio2-width another 10 and in total we >> have 20 gpios. > > OK that is confusing. Let's not do that then. > >> I think that it is better not to start to mess with ngpios property not >> to confuse people which are coming from other SOCs because ngpios can >> suggest all gpios assigned to this controller. > > OK I agree. > >>>> + if (chip->gpio_width[0] > 32) >>>> + return -EINVAL; >>> >>> This looks OK. >> >> Does it mean ack for this patch? > > Yeah after explanations this patch is fine: > Acked-by: Linus Walleij > > It's just that this hardware with paired controllers is a bit weird so it will > lead to discussions all the time because it's hard to understand. Maybe it should be described a little bit differently in DT. Just to have gpio node and every bank could be described as a child node where standard properties could be used and irq will be shared. Thanks, Michal