From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2CDDC433EF for ; Fri, 24 Jun 2022 12:58:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232012AbiFXM6G (ORCPT ); Fri, 24 Jun 2022 08:58:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230100AbiFXM6D (ORCPT ); Fri, 24 Jun 2022 08:58:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A722D2739 for ; Fri, 24 Jun 2022 05:58:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4059461DF2 for ; Fri, 24 Jun 2022 12:58:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A62E9C341CA for ; Fri, 24 Jun 2022 12:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656075480; bh=/ahIzyQOHG0m+SQ+jq1EI2q1DZMia1Faeq4hY5WIHGA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=P6mT20aDdOSEQW7u1UjSzfBq3fbS4zWQecGaf2Zy7GiiNyNkEDtFX7LYYOWjfqqoS bIKXnkDrasjX0YIaEhjfusyeqIDwQs+j8nPlQVuFQxLMQVFOWwzu6TpGHJpfF9UuEP l6qYToiXUmCXyrW/IRR5SuZKgCEbUzB7+6nLqBrqZZioKp6/2mL9k8BsuWbGZFsEAu gZGEtdukdR6Rqmo4hF0M8TBNVffZlRcQ+l1i+eg0ji07bgCTM0I1XVfqj3nHkDzFAI NWL8feTdp1ql8RF+pZkKhp0FV/6xz8KM4MfgSWeHytislaDnTMseW2yMnuG8Gsmxml lvVCCwxIPttwg== Received: by mail-oi1-f182.google.com with SMTP id u189so3522653oib.4 for ; Fri, 24 Jun 2022 05:58:00 -0700 (PDT) X-Gm-Message-State: AJIora8rYw5zBgaO5IJEwCcl93jF6hu4oIW6UGVBqQkpAH4RNMJsVP2B qd+JD1zvpPOInNAevIxrj1oooLz555KB8BVhpTM= X-Google-Smtp-Source: AGRyM1us/I0uZmsaDDAvmLrTpbwS1EbTLH5Tm01RPd967T0ifV9s2JyO8+KuVX1DAmGaFTRppla6Ohp88pZvhS7LScM= X-Received: by 2002:a05:6808:300e:b0:32c:425e:df34 with SMTP id ay14-20020a056808300e00b0032c425edf34mr1883403oib.126.1656075479794; Fri, 24 Jun 2022 05:57:59 -0700 (PDT) MIME-Version: 1.0 References: <20220613144550.3760857-1-ardb@kernel.org> <20220613144550.3760857-4-ardb@kernel.org> <20220624123602.GC18561@willie-the-truck> In-Reply-To: <20220624123602.GC18561@willie-the-truck> From: Ard Biesheuvel Date: Fri, 24 Jun 2022 14:57:48 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 03/26] arm64: head: move assignment of idmap_t0sz to C code To: Will Deacon Cc: Linux ARM , linux-hardening@vger.kernel.org, Marc Zyngier , Mark Rutland , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org On Fri, 24 Jun 2022 at 14:36, Will Deacon wrote: > > On Mon, Jun 13, 2022 at 04:45:27PM +0200, Ard Biesheuvel wrote: > > Setting idmap_t0sz involves fiddling with the caches if done with the > > MMU off. Since we will be creating an initial ID map with the MMU and > > caches off, and the permanent ID map with the MMU and caches on, let's > > move this assignment of idmap_t0sz out of the startup code, and replace > > it with a macro that simply issues the three instructions needed to > > calculate the value wherever it is needed before the MMU is turned on. > > > > Signed-off-by: Ard Biesheuvel > > --- > > arch/arm64/include/asm/assembler.h | 14 ++++++++++++++ > > arch/arm64/include/asm/mmu_context.h | 2 +- > > arch/arm64/kernel/head.S | 13 +------------ > > arch/arm64/mm/mmu.c | 5 ++++- > > arch/arm64/mm/proc.S | 2 +- > > 5 files changed, 21 insertions(+), 15 deletions(-) > > > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > > index 8c5a61aeaf8e..9468f45c07a6 100644 > > --- a/arch/arm64/include/asm/assembler.h > > +++ b/arch/arm64/include/asm/assembler.h > > @@ -359,6 +359,20 @@ alternative_cb_end > > bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH > > .endm > > > > +/* > > + * idmap_get_t0sz - get the T0SZ value needed to cover the ID map > > + * > > + * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the > > + * entire ID map region can be mapped. As T0SZ == (64 - #bits used), > > + * this number conveniently equals the number of leading zeroes in > > + * the physical address of _end. > > + */ > > + .macro idmap_get_t0sz, reg > > + adrp \reg, _end > > + orr \reg, \reg, #(1 << VA_BITS_MIN) - 1 > > + clz \reg, \reg > > + .endm > > + > > /* > > * tcr_compute_pa_size - set TCR.(I)PS to the highest supported > > * ID_AA64MMFR0_EL1.PARange value > > diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h > > index 6770667b34a3..6ac0086ebb1a 100644 > > --- a/arch/arm64/include/asm/mmu_context.h > > +++ b/arch/arm64/include/asm/mmu_context.h > > @@ -60,7 +60,7 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) > > * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in > > * physical memory, in which case it will be smaller. > > */ > > -extern u64 idmap_t0sz; > > +extern int idmap_t0sz; > > extern u64 idmap_ptrs_per_pgd; > > > > /* > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > > index dc07858eb673..7f361bc72d12 100644 > > --- a/arch/arm64/kernel/head.S > > +++ b/arch/arm64/kernel/head.S > > @@ -299,22 +299,11 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > > * physical address space. So for the ID map, use an extended virtual > > * range in that case, and configure an additional translation level > > * if needed. > > - * > > - * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the > > - * entire ID map region can be mapped. As T0SZ == (64 - #bits used), > > - * this number conveniently equals the number of leading zeroes in > > - * the physical address of __idmap_text_end. > > */ > > - adrp x5, __idmap_text_end > > - clz x5, x5 > > + idmap_get_t0sz x5 > > cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? > > b.ge 1f // .. then skip VA range extension > > > > - adr_l x6, idmap_t0sz > > - str x5, [x6] > > - dmb sy > > - dc ivac, x6 // Invalidate potentially stale cache line > > - > > #if (VA_BITS < 48) > > #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) > > #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) > > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c > > index 17b339c1a326..103bf4ae408d 100644 > > --- a/arch/arm64/mm/mmu.c > > +++ b/arch/arm64/mm/mmu.c > > @@ -43,7 +43,7 @@ > > #define NO_CONT_MAPPINGS BIT(1) > > #define NO_EXEC_MAPPINGS BIT(2) /* assumes FEAT_HPDS is not used */ > > > > -u64 idmap_t0sz = TCR_T0SZ(VA_BITS_MIN); > > +int idmap_t0sz __ro_after_init; > > u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; > > > > #if VA_BITS > 48 > > @@ -785,6 +785,9 @@ void __init paging_init(void) > > (u64)&vabits_actual + sizeof(vabits_actual)); > > #endif > > > > + idmap_t0sz = min(63UL - __fls(__pa_symbol(_end)), > > + TCR_T0SZ(VA_BITS_MIN)); > > nit: TCR_T0SZ shifts by TCR_T0SZ_OFFSET, so this is a bit confusing and > works out because the register offset happens to be zero. Maybe it would > be clearer to calculate the maximum of fls(__pa_symbol(_end)) and > VA_BITS_MIN, then subtract that from 64? > I just noticed there are other inconsistencies with TCR_T0SZ(), e.g., in create_safe_exec_page(), which receives the 'shifted' value of t0sz, but then shifts it again in cpu_install_ttbr0(). So this is definitely Let's just use the same expression as in the idmap_get_t0sz macro I am adding: idmap_t0sz = 63UL - __fls(__pa_symbol(_end) | GENMASK(VA_BITS_MIN - 1, 0));