From: Andrea Parri <parri.andrea@gmail.com>
To: linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org,
x86@kernel.org
Cc: "K . Y . Srinivasan" <kys@microsoft.com>,
Haiyang Zhang <haiyangz@microsoft.com>,
Stephen Hemminger <sthemmin@microsoft.com>,
Sasha Levin <sashal@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H . Peter Anvin" <hpa@zytor.com>,
Michael Kelley <mikelley@microsoft.com>
Subject: Re: [PATCH 1/2] x86/hyperv: Allow guests to enable InvariantTSC
Date: Thu, 3 Oct 2019 18:03:26 +0200 [thread overview]
Message-ID: <20191003160326.GA22098@andrea.guest.corp.microsoft.com> (raw)
In-Reply-To: <20191003155200.22022-1-parri.andrea@gmail.com>
On Thu, Oct 03, 2019 at 05:52:00PM +0200, Andrea Parri wrote:
> If the hardware supports TSC scaling, Hyper-V will set bit 15 of the
> HV_PARTITION_PRIVILEGE_MASK in guest VMs with a compatible Hyper-V
> configuration version. Bit 15 corresponds to the
> AccessTscInvariantControls privilege. If this privilege bit is set,
> guests can access the HvSyntheticInvariantTscControl MSR: guests can
> set bit 0 of this synthetic MSR to enable the InvariantTSC feature.
> After setting the synthetic MSR, CPUID will enumerate support for
> InvariantTSC.
>
> Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Subject should have been "[PATCH] ...", i.e., there is no 2/2 planned
(not for this patchset at least). Please let me know if I should re-
submit with the subject fixed.
Thanks,
Andrea
next prev parent reply other threads:[~2019-10-03 17:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 15:52 [PATCH 1/2] x86/hyperv: Allow guests to enable InvariantTSC Andrea Parri
2019-10-03 16:03 ` Andrea Parri [this message]
2019-10-03 23:15 ` Michael Kelley
2019-10-04 16:57 ` Vitaly Kuznetsov
2019-10-04 22:05 ` Michael Kelley
2019-10-08 15:12 ` Vitaly Kuznetsov
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