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[91.219.240.2]) by smtp.gmail.com with ESMTPSA id dj16sm3781486edb.0.2021.07.16.06.25.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 06:25:57 -0700 (PDT) From: Vitaly Kuznetsov To: Ani Sinha , linux-kernel@vger.kernel.org Cc: anirban.sinha@nokia.com, mikelley@microsoft.com, Ani Sinha , "K. Y. Srinivasan" , Haiyang Zhang , Stephen Hemminger , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , linux-hyperv@vger.kernel.org Subject: Re: [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0 In-Reply-To: <20210716063341.2865562-1-ani@anisinha.ca> References: <20210716063341.2865562-1-ani@anisinha.ca> Date: Fri, 16 Jul 2021 15:25:55 +0200 Message-ID: <8735se1jbw.fsf@vitty.brq.redhat.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org Ani Sinha writes: > Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC") > added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0 > of this synthetic MSR will allow hyper-v guests to report invariant TSC > CPU feature through CPUID. This comment adds this explanation to the code > and mentions where the Intel's generic platform init code reads this > feature bit from CPUID. The comment will help developers understand how > the two parts of the initialization (hyperV specific and non-hyperV > specific generic hw init) are related. > > Signed-off-by: Ani Sinha > --- > arch/x86/kernel/cpu/mshyperv.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c > index 715458b7729a..d2429748170d 100644 > --- a/arch/x86/kernel/cpu/mshyperv.c > +++ b/arch/x86/kernel/cpu/mshyperv.c > @@ -368,6 +368,14 @@ static void __init ms_hyperv_init_platform(void) > machine_ops.crash_shutdown = hv_machine_crash_shutdown; > #endif > if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { > + /* > + * Setting bit 0 of the synthetic MSR 0x40000118 enables > + * guests to report invariant TSC feature through CPUID > + * instruction, CPUID 0x800000007/EDX, bit 8. See code in > + * early_init_intel() where this bit is examined. The > + * setting of this MSR bit should happen before init_intel() > + * is called. It should probably be emphasized, that write to 0x40000118 updates/changes guest visible CPUIDs. This may not be clear as CPUIDs are generally considered 'static'. > + */ > wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1); > setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); > } -- Vitaly