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b=Zy9214k2eBE9m1k778qA0iRLDZ/dcmkh03niPXUup8iPpajANtg2M56D7zP7xZsi24Y2FXsdR3Wf9Rsxgt0CNRJVD5OFVHApRAMpuqOA1C3fRBWYFKYupj9wLv4JVnL5wuA6JMC3LOi1rwTstcBGH9ZSQnAMDZZ1IPM9JZqygwU= Received: from BYAPR21MB1688.namprd21.prod.outlook.com (2603:10b6:a02:bf::26) by MN0PR21MB3749.namprd21.prod.outlook.com (2603:10b6:208:3d1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.1; Tue, 3 Jan 2023 19:11:30 +0000 Received: from BYAPR21MB1688.namprd21.prod.outlook.com ([fe80::db1a:4e71:c688:b7b1]) by BYAPR21MB1688.namprd21.prod.outlook.com ([fe80::db1a:4e71:c688:b7b1%4]) with mapi id 15.20.6002.005; Tue, 3 Jan 2023 19:11:30 +0000 From: "Michael Kelley (LINUX)" To: Jinank Jain , Jinank Jain CC: KY Srinivasan , Haiyang Zhang , "wei.liu@kernel.org" , Dexuan Cui , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "arnd@arndb.de" , "peterz@infradead.org" , "jpoimboe@kernel.org" , "seanjc@google.com" , "kirill.shutemov@linux.intel.com" , "ak@linux.intel.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "linux-hyperv@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arch@vger.kernel.org" , "anrayabh@linux.microsoft.com" Subject: RE: [PATCH v10 2/5] Drivers: hv: Setup synic registers in case of nested root partition Thread-Topic: [PATCH v10 2/5] Drivers: hv: Setup synic registers in case of nested root partition Thread-Index: AQHZHnmpvVLD+m3uzEu9T0k4Q2fsXa6Ktk4AgAJaq9A= Date: Tue, 3 Jan 2023 19:11:30 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ActionId=4cc76ffc-1500-4fa0-b5fd-4f24d6395506;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ContentBits=0;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=true;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Method=Standard;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Name=Internal;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2023-01-03T19:09:54Z;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SiteId=72f988bf-86f1-41af-91ab-2d7cd011db47; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR21MB1688.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 871316f4-b10a-4fd5-e424-08daedbe520a X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jan 2023 19:11:30.1736 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QwbLCwzKBwVpa7sIgCmIjdA8pc1BK/HixR8JdXDxIY8cek478w4ZfqXaFVO+yd1LVlstGvJ3j4lx9H3SnyyNlBuO1/pZ0/WZzYIVBzgJK1k= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR21MB3749 Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org From: Jinank Jain Sent: Sunday, January 1,= 2023 11:13 PM >=20 > Child partitions are free to allocate SynIC message and event page but in > case of root partition it must use the pages allocated by Microsoft > Hypervisor (MSHV). Base address for these pages can be found using > synthetic MSRs exposed by MSHV. There is a slight difference in those MSR= s > for nested vs non-nested root partition. >=20 > Signed-off-by: Jinank Jain > --- > arch/x86/include/asm/hyperv-tlfs.h | 11 +++++ > arch/x86/include/asm/mshyperv.h | 30 +++----------- > arch/x86/kernel/cpu/mshyperv.c | 65 ++++++++++++++++++++++++++++++ > drivers/hv/hv.c | 18 +++++---- > 4 files changed, 93 insertions(+), 31 deletions(-) >=20 > diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hy= perv-tlfs.h > index 58c03d18c235..b5019becb618 100644 > --- a/arch/x86/include/asm/hyperv-tlfs.h > +++ b/arch/x86/include/asm/hyperv-tlfs.h > @@ -225,6 +225,17 @@ enum hv_isolation_type { > #define HV_REGISTER_SINT14 0x4000009E > #define HV_REGISTER_SINT15 0x4000009F >=20 > +/* > + * Define synthetic interrupt controller model specific registers for > + * nested hypervisor. > + */ > +#define HV_REGISTER_NESTED_SCONTROL 0x40001080 > +#define HV_REGISTER_NESTED_SVERSION 0x40001081 > +#define HV_REGISTER_NESTED_SIEFP 0x40001082 > +#define HV_REGISTER_NESTED_SIMP 0x40001083 > +#define HV_REGISTER_NESTED_EOM 0x40001084 > +#define HV_REGISTER_NESTED_SINT0 0x40001090 > + > /* > * Synthetic Timer MSRs. Four timers per vcpu. > */ > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyp= erv.h > index 61f0c206bff0..c38e4c66a3ac 100644 > --- a/arch/x86/include/asm/mshyperv.h > +++ b/arch/x86/include/asm/mshyperv.h > @@ -198,30 +198,10 @@ static inline bool hv_is_synic_reg(unsigned int reg= ) > return false; > } >=20 > -static inline u64 hv_get_register(unsigned int reg) > -{ > - u64 value; > - > - if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) > - hv_ghcb_msr_read(reg, &value); > - else > - rdmsrl(reg, value); > - return value; > -} > - > -static inline void hv_set_register(unsigned int reg, u64 value) > -{ > - if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) { > - hv_ghcb_msr_write(reg, value); > - > - /* Write proxy bit via wrmsl instruction */ > - if (reg >=3D HV_REGISTER_SINT0 && > - reg <=3D HV_REGISTER_SINT15) > - wrmsrl(reg, value | 1 << 20); > - } else { > - wrmsrl(reg, value); > - } > -} > +u64 hv_get_register(unsigned int reg); > +void hv_set_register(unsigned int reg, u64 value); > +u64 hv_get_non_nested_register(unsigned int reg); > +void hv_set_non_nested_register(unsigned int reg, u64 value); >=20 > #else /* CONFIG_HYPERV */ > static inline void hyperv_init(void) {} > @@ -241,6 +221,8 @@ static inline int hyperv_flush_guest_mapping_range(u6= 4 as, > } > static inline void hv_set_register(unsigned int reg, u64 value) { } > static inline u64 hv_get_register(unsigned int reg) { return 0; } > +static inline void hv_set_non_nested_register(unsigned int reg, u64 valu= e) { } > +static inline u64 hv_get_non_nested_register(unsigned int reg) { return = 0; } > static inline int hv_set_mem_host_visibility(unsigned long addr, int num= pages, > bool visible) > { > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyper= v.c > index f9b78d4829e3..938fc82edf05 100644 > --- a/arch/x86/kernel/cpu/mshyperv.c > +++ b/arch/x86/kernel/cpu/mshyperv.c > @@ -41,7 +41,72 @@ bool hv_root_partition; > bool hv_nested; > struct ms_hyperv_info ms_hyperv; >=20 > +static inline unsigned int hv_get_nested_reg(unsigned int reg) > +{ > + switch (reg) { > + case HV_REGISTER_SIMP: > + return HV_REGISTER_NESTED_SIMP; > + case HV_REGISTER_SIEFP: > + return HV_REGISTER_NESTED_SIEFP; > + case HV_REGISTER_SVERSION: > + return HV_REGISTER_NESTED_SVERSION; > + case HV_REGISTER_SCONTROL: > + return HV_REGISTER_NESTED_SCONTROL; > + case HV_REGISTER_SINT0: > + return HV_REGISTER_NESTED_SINT0; > + case HV_REGISTER_EOM: > + return HV_REGISTER_NESTED_EOM; > + default: > + return reg; > + } > +} > + > #if IS_ENABLED(CONFIG_HYPERV) > +u64 hv_get_non_nested_register(unsigned int reg) > +{ > + u64 value; > + > + if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) > + hv_ghcb_msr_read(reg, &value); > + else > + rdmsrl(reg, value); > + return value; > +} > +EXPORT_SYMBOL_GPL(hv_get_non_nested_register); > + > +void hv_set_non_nested_register(unsigned int reg, u64 value) > +{ > + if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) { > + hv_ghcb_msr_write(reg, value); > + > + /* Write proxy bit via wrmsl instruction */ > + if (reg >=3D HV_REGISTER_SINT0 && > + reg <=3D HV_REGISTER_SINT15) > + wrmsrl(reg, value | 1 << 20); > + } else { > + wrmsrl(reg, value); > + } > +} > +EXPORT_SYMBOL_GPL(hv_set_non_nested_register); > + > +u64 hv_get_register(unsigned int reg) > +{ > + if (hv_nested) > + reg =3D hv_get_nested_reg(reg); > + > + return hv_get_non_nested_register(reg); > +} > +EXPORT_SYMBOL_GPL(hv_get_register); > + > +void hv_set_register(unsigned int reg, u64 value) > +{ > + if (hv_nested) > + reg =3D hv_get_nested_reg(reg); > + > + hv_set_non_nested_register(reg, value); > +} > +EXPORT_SYMBOL_GPL(hv_set_register); > + > static void (*vmbus_handler)(void); > static void (*hv_stimer0_handler)(void); > static void (*hv_kexec_handler)(void); > diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c > index 4d6480d57546..8b0dd8e5244d 100644 > --- a/drivers/hv/hv.c > +++ b/drivers/hv/hv.c > @@ -147,7 +147,7 @@ int hv_synic_alloc(void) > * Synic message and event pages are allocated by paravisor. > * Skip these pages allocation here. > */ > - if (!hv_isolation_type_snp()) { > + if (!hv_isolation_type_snp() && !hv_root_partition) { > hv_cpu->synic_message_page =3D > (void *)get_zeroed_page(GFP_ATOMIC); > if (hv_cpu->synic_message_page =3D=3D NULL) { > @@ -216,7 +216,7 @@ void hv_synic_enable_regs(unsigned int cpu) > simp.as_uint64 =3D hv_get_register(HV_REGISTER_SIMP); > simp.simp_enabled =3D 1; >=20 > - if (hv_isolation_type_snp()) { > + if (hv_isolation_type_snp() || hv_root_partition) { > hv_cpu->synic_message_page > =3D memremap(simp.base_simp_gpa << HV_HYP_PAGE_SHIFT, > HV_HYP_PAGE_SIZE, MEMREMAP_WB); > @@ -233,7 +233,7 @@ void hv_synic_enable_regs(unsigned int cpu) > siefp.as_uint64 =3D hv_get_register(HV_REGISTER_SIEFP); > siefp.siefp_enabled =3D 1; >=20 > - if (hv_isolation_type_snp()) { > + if (hv_isolation_type_snp() || hv_root_partition) { > hv_cpu->synic_event_page =3D > memremap(siefp.base_siefp_gpa << HV_HYP_PAGE_SHIFT, > HV_HYP_PAGE_SIZE, MEMREMAP_WB); > @@ -315,20 +315,24 @@ void hv_synic_disable_regs(unsigned int cpu) > * addresses. > */ > simp.simp_enabled =3D 0; > - if (hv_isolation_type_snp()) > + if (hv_isolation_type_snp() || hv_root_partition) { > memunmap(hv_cpu->synic_message_page); > - else > + hv_cpu->synic_message_page =3D NULL; > + } else { > simp.base_simp_gpa =3D 0; > + } >=20 > hv_set_register(HV_REGISTER_SIMP, simp.as_uint64); >=20 > siefp.as_uint64 =3D hv_get_register(HV_REGISTER_SIEFP); > siefp.siefp_enabled =3D 0; >=20 > - if (hv_isolation_type_snp()) > + if (hv_isolation_type_snp() || hv_root_partition) { > memunmap(hv_cpu->synic_event_page); > - else > + hv_cpu->synic_event_page =3D NULL; > + } else { > siefp.base_siefp_gpa =3D 0; > + } >=20 > hv_set_register(HV_REGISTER_SIEFP, siefp.as_uint64); >=20 > -- > 2.25.1 Looks good! Thanks for persisting and addressing my concerns. Reviewed-by: Michael Kelley