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Mon, 13 Sep 2021 17:36:47 +0000 From: Sunil Muthuswamy To: Michael Kelley , Boqun Feng , KY Srinivasan , Haiyang Zhang , Stephen Hemminger , Dexuan Cui , Lorenzo Pieralisi , Rob Herring , =?iso-8859-2?Q?=22Krzysztof_Wilczy=F1ski=22?= , Bjorn Helgaas , Wei Liu CC: "linux-hyperv@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 1/2] PCI: hv: Make the code arch neutral Thread-Topic: [PATCH 1/2] PCI: hv: Make the code arch neutral Thread-Index: AdeoxSGQR+XTDCnuQJejgIDf8UzhEg== Date: Mon, 13 Sep 2021 17:36:46 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microsoft.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a4fa2991-034c-423e-c0f3-08d976dd0ffc x-ms-traffictypediagnostic: MWHPR21MB0830: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR21MB2002.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a4fa2991-034c-423e-c0f3-08d976dd0ffc X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Sep 2021 17:36:46.9225 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dmWAksxVL+vkvdyDzSckacIUhdD//L39cZCzC2HHa39IX5iit+X/PypnJM7hH1WR5SrFBRZzwXq1AqL/c6xW5H4eRGvIhzf9LMPYDtcxa2Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR21MB0830 Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org This patch makes the Hyper-V vPCI code architectural neutral by moving the architectural dependent pieces into arch specific code. This allows for the implementation of Hyper-V vPCI for other architecture such as ARM64. There are no functional changes expected from this patch. Signed-off-by: Sunil Muthuswamy --- arch/x86/include/asm/hyperv-tlfs.h | 33 ++++++++++++++++++++++ arch/x86/include/asm/mshyperv.h | 25 ++++++++++++++++ drivers/pci/controller/pci-hyperv.c | 44 +++++++++++++++++++---------- include/asm-generic/hyperv-tlfs.h | 33 ---------------------- 4 files changed, 87 insertions(+), 48 deletions(-) diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hype= rv-tlfs.h index 2322d6bd5883..fdf3d28fbdd5 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -585,6 +585,39 @@ enum hv_interrupt_type { HV_X64_INTERRUPT_TYPE_MAXIMUM =3D 0x000A, }; =20 +union hv_msi_address_register { + u32 as_uint32; + struct { + u32 reserved1:2; + u32 destination_mode:1; + u32 redirection_hint:1; + u32 reserved2:8; + u32 destination_id:8; + u32 msi_base:12; + }; +} __packed; + +union hv_msi_data_register { + u32 as_uint32; + struct { + u32 vector:8; + u32 delivery_mode:3; + u32 reserved1:3; + u32 level_assert:1; + u32 trigger_mode:1; + u32 reserved2:16; + }; +} __packed; + +/* HvRetargetDeviceInterrupt hypercall */ +union hv_msi_entry { + u64 as_uint64; + struct { + union hv_msi_address_register address; + union hv_msi_data_register data; + } __packed; +}; + #include =20 #endif diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyper= v.h index adccbc209169..9c53dfef360c 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -10,6 +10,7 @@ #include #include #include +#include =20 typedef int (*hyperv_fill_flush_list_func)( struct hv_guest_mapping_flush_list *flush, @@ -168,6 +169,30 @@ int hyperv_fill_flush_guest_mapping_list( struct hv_guest_mapping_flush_list *flush, u64 start_gfn, u64 end_gfn); =20 +#define hv_msi_handler handle_edge_irq +#define hv_msi_handler_name "edge" +#define hv_msi_prepare pci_msi_prepare +#define hv_msi_irq_delivery_mode APIC_DELIVERY_MODE_FIXED + +static inline struct irq_domain *hv_msi_parent_vector_domain(void) +{ + return x86_vector_domain; +} + +static inline unsigned int hv_msi_get_int_vector(struct irq_data *data) +{ + struct irq_cfg *cfg =3D irqd_cfg(data); + + return cfg->vector; +} + +static inline int hv_pci_arch_init(void) +{ + return 0; +} + +static inline void hv_pci_arch_free(void) {} + #ifdef CONFIG_X86_64 void hv_apic_init(void); void __init hv_init_spinlocks(void); diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/p= ci-hyperv.c index 62dbe98d1fe1..b7213b57b4ec 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -44,8 +44,8 @@ #include #include #include -#include -#include +//#include +//#include #include #include #include @@ -1192,7 +1192,6 @@ static void hv_irq_mask(struct irq_data *data) static void hv_irq_unmask(struct irq_data *data) { struct msi_desc *msi_desc =3D irq_data_get_msi_desc(data); - struct irq_cfg *cfg =3D irqd_cfg(data); struct hv_retarget_device_interrupt *params; struct hv_pcibus_device *hbus; struct cpumask *dest; @@ -1221,11 +1220,12 @@ static void hv_irq_unmask(struct irq_data *data) (hbus->hdev->dev_instance.b[7] << 8) | (hbus->hdev->dev_instance.b[6] & 0xf8) | PCI_FUNC(pdev->devfn); - params->int_target.vector =3D cfg->vector; + params->int_target.vector =3D hv_msi_get_int_vector(data); =20 /* - * Honoring apic->delivery_mode set to APIC_DELIVERY_MODE_FIXED by - * setting the HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a + * For x64, honoring apic->delivery_mode set to + * APIC_DELIVERY_MODE_FIXED by setting the + * HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a * spurious interrupt storm. Not doing so does not seem to have a * negative effect (yet?). */ @@ -1322,7 +1322,7 @@ static u32 hv_compose_msi_req_v1( int_pkt->wslot.slot =3D slot; int_pkt->int_desc.vector =3D vector; int_pkt->int_desc.vector_count =3D 1; - int_pkt->int_desc.delivery_mode =3D APIC_DELIVERY_MODE_FIXED; + int_pkt->int_desc.delivery_mode =3D hv_msi_irq_delivery_mode; =20 /* * Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in @@ -1343,7 +1343,7 @@ static u32 hv_compose_msi_req_v2( int_pkt->wslot.slot =3D slot; int_pkt->int_desc.vector =3D vector; int_pkt->int_desc.vector_count =3D 1; - int_pkt->int_desc.delivery_mode =3D APIC_DELIVERY_MODE_FIXED; + int_pkt->int_desc.delivery_mode =3D hv_msi_irq_delivery_mode; =20 /* * Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten @@ -1370,7 +1370,6 @@ static u32 hv_compose_msi_req_v2( */ static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct irq_cfg *cfg =3D irqd_cfg(data); struct hv_pcibus_device *hbus; struct vmbus_channel *channel; struct hv_pci_dev *hpdev; @@ -1420,7 +1419,7 @@ static void hv_compose_msi_msg(struct irq_data *data,= struct msi_msg *msg) size =3D hv_compose_msi_req_v1(&ctxt.int_pkts.v1, dest, hpdev->desc.win_slot.slot, - cfg->vector); + hv_msi_get_int_vector(data)); break; =20 case PCI_PROTOCOL_VERSION_1_2: @@ -1428,7 +1427,7 @@ static void hv_compose_msi_msg(struct irq_data *data,= struct msi_msg *msg) size =3D hv_compose_msi_req_v2(&ctxt.int_pkts.v2, dest, hpdev->desc.win_slot.slot, - cfg->vector); + hv_msi_get_int_vector(data)); break; =20 default: @@ -1544,7 +1543,7 @@ static struct irq_chip hv_msi_irq_chip =3D { }; =20 static struct msi_domain_ops hv_msi_ops =3D { - .msi_prepare =3D pci_msi_prepare, + .msi_prepare =3D hv_msi_prepare, .msi_free =3D hv_msi_free, }; =20 @@ -1563,17 +1562,26 @@ static struct msi_domain_ops hv_msi_ops =3D { */ static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus) { + struct irq_domain *parent_domain; + + parent_domain =3D hv_msi_parent_vector_domain(); + if (!parent_domain) { + dev_err(&hbus->hdev->device, + "Failed to get parent MSI domain\n"); + return -ENODEV; + } + hbus->msi_info.chip =3D &hv_msi_irq_chip; hbus->msi_info.ops =3D &hv_msi_ops; hbus->msi_info.flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX); - hbus->msi_info.handler =3D handle_edge_irq; - hbus->msi_info.handler_name =3D "edge"; + hbus->msi_info.handler =3D hv_msi_handler; + hbus->msi_info.handler_name =3D hv_msi_handler_name; hbus->msi_info.data =3D hbus; hbus->irq_domain =3D pci_msi_create_irq_domain(hbus->fwnode, &hbus->msi_info, - x86_vector_domain); + parent_domain); if (!hbus->irq_domain) { dev_err(&hbus->hdev->device, "Failed to build an MSI IRQ domain\n"); @@ -3478,9 +3486,15 @@ static void __exit exit_hv_pci_drv(void) =20 static int __init init_hv_pci_drv(void) { + int ret; + if (!hv_is_hyperv_initialized()) return -ENODEV; =20 + ret =3D hv_pci_arch_init(); + if (ret) + return ret; + /* Set the invalid domain number's bit, so it will not be used */ set_bit(HVPCI_DOM_INVALID, hvpci_dom_map); =20 diff --git a/include/asm-generic/hyperv-tlfs.h b/include/asm-generic/hyperv= -tlfs.h index 56348a541c50..45cc0c3b8ed7 100644 --- a/include/asm-generic/hyperv-tlfs.h +++ b/include/asm-generic/hyperv-tlfs.h @@ -539,39 +539,6 @@ enum hv_interrupt_source { HV_INTERRUPT_SOURCE_IOAPIC, }; =20 -union hv_msi_address_register { - u32 as_uint32; - struct { - u32 reserved1:2; - u32 destination_mode:1; - u32 redirection_hint:1; - u32 reserved2:8; - u32 destination_id:8; - u32 msi_base:12; - }; -} __packed; - -union hv_msi_data_register { - u32 as_uint32; - struct { - u32 vector:8; - u32 delivery_mode:3; - u32 reserved1:3; - u32 level_assert:1; - u32 trigger_mode:1; - u32 reserved2:16; - }; -} __packed; - -/* HvRetargetDeviceInterrupt hypercall */ -union hv_msi_entry { - u64 as_uint64; - struct { - union hv_msi_address_register address; - union hv_msi_data_register data; - } __packed; -}; - union hv_ioapic_rte { u64 as_uint64; =20 --=20 2.25.1