From: Michael Kelley <mikelley@microsoft.com>
To: Ani Sinha <ani@anisinha.ca>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "anirban.sinha@nokia.com" <anirban.sinha@nokia.com>,
KY Srinivasan <kys@microsoft.com>,
Haiyang Zhang <haiyangz@microsoft.com>,
Stephen Hemminger <sthemmin@microsoft.com>,
Wei Liu <wei.liu@kernel.org>, Dexuan Cui <decui@microsoft.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"x86@kernel.org" <x86@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>,
"linux-hyperv@vger.kernel.org" <linux-hyperv@vger.kernel.org>
Subject: RE: [PATCH v2] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
Date: Fri, 16 Jul 2021 13:59:33 +0000 [thread overview]
Message-ID: <MWHPR21MB1593767AA88C7FD60A476DC2D7119@MWHPR21MB1593.namprd21.prod.outlook.com> (raw)
In-Reply-To: <20210716133245.3272672-1-ani@anisinha.ca>
From: Ani Sinha <ani@anisinha.ca> Sent: Friday, July 16, 2021 6:33 AM
>
> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
>
> Signed-off-by: Ani Sinha <ani@anisinha.ca>
> ---
> arch/x86/kernel/cpu/mshyperv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> changelog:
> v1: initial patch
> v2: slight comment update based on received feedback.
>
> diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> index 715458b7729a..3b05dab3086e 100644
> --- a/arch/x86/kernel/cpu/mshyperv.c
> +++ b/arch/x86/kernel/cpu/mshyperv.c
> @@ -368,6 +368,15 @@ static void __init ms_hyperv_init_platform(void)
> machine_ops.crash_shutdown = hv_machine_crash_shutdown;
> #endif
> if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
> + /*
> + * Writing to synthetic MSR 0x40000118 updates/changes the
> + * guest visible CPUIDs. Setting bit 0 of this MSR enables
> + * guests to report invariant TSC feature through CPUID
> + * instruction, CPUID 0x800000007/EDX, bit 8. See code in
> + * early_init_intel() where this bit is examined. The
> + * setting of this MSR bit should happen before init_intel()
> + * is called.
> + */
> wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
> setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> }
> --
> 2.25.1
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
next prev parent reply other threads:[~2021-07-16 13:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 13:32 [PATCH v2] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0 Ani Sinha
2021-07-16 13:42 ` Vitaly Kuznetsov
2021-07-16 13:59 ` Michael Kelley [this message]
2021-07-16 14:53 ` Wei Liu
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