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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR21MB1593.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0e72934f-5ce0-42d1-a601-08d9a5765f2b X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Nov 2021 00:50:06.9756 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kpBa4wsM+oEEm1i7+TNeDzpAYkGnbDKN9d53VPVgd8hL9zV6spyzMYsstXFizferB+BzxVXmQI3u2MXAnRgFTXfa4SX1wc6h3wXNoN3q1SA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR21MB1969 Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org From: Sunil Muthuswamy Sent: Wednesday, Nove= mber 10, 2021 11:45 AM >=20 > Add support for Hyper-V vPCI for arm64 by implementing the arch specific > interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI tha= t > is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domai= n > for basic vector management. >=20 > Signed-off-by: Sunil Muthuswamy > --- > In v2, v3, v4 & v5: > Changes are described in the cover letter. >=20 > arch/arm64/include/asm/hyperv-tlfs.h | 9 ++ > drivers/pci/Kconfig | 2 +- > drivers/pci/controller/Kconfig | 2 +- > drivers/pci/controller/pci-hyperv.c | 204 ++++++++++++++++++++++++++- > 4 files changed, 214 insertions(+), 3 deletions(-) >=20 [snip] > diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller= /pci-hyperv.c > index 03e07a4f0e3f..b13e3ae5a34f 100644 > --- a/drivers/pci/controller/pci-hyperv.c > +++ b/drivers/pci/controller/pci-hyperv.c > @@ -47,6 +47,8 @@ > #include > #include > #include > +#include > +#include > #include >=20 > /* > @@ -614,7 +616,202 @@ static int hv_msi_prepare(struct irq_domain *domain= , struct device *dev, > { > return pci_msi_prepare(domain, dev, nvec, info); > } > -#endif // CONFIG_X86 > +#elif defined(CONFIG_ARM64) > +/* > + * SPI vectors to use for vPCI; arch SPIs range is [32, 1019], but leavi= ng a bit > + * of room at the start to allow for SPIs to be specified through ACPI a= nd > + * starting with a power of two to satisfy power of 2 multi-MSI requirem= ent. > + */ > +#define HV_PCI_MSI_SPI_START 64 > +#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START) > +#define DELIVERY_MODE 0 > +#define FLOW_HANDLER NULL > +#define FLOW_NAME NULL > +#define hv_msi_prepare NULL > + > +struct hv_pci_chip_data { > + DECLARE_BITMAP(spi_map, HV_PCI_MSI_SPI_NR); > + struct mutex map_lock; > +}; > + > +/* Hyper-V vPCI MSI GIC IRQ domain */ > +static struct irq_domain *hv_msi_gic_irq_domain; > + > +/* Hyper-V PCI MSI IRQ chip */ > +static struct irq_chip hv_arm64_msi_irq_chip =3D { > + .name =3D "MSI", > + .irq_set_affinity =3D irq_chip_set_affinity_parent, > + .irq_eoi =3D irq_chip_eoi_parent, > + .irq_mask =3D irq_chip_mask_parent, > + .irq_unmask =3D irq_chip_unmask_parent > +}; > + > +static unsigned int hv_msi_get_int_vector(struct irq_data *irqd) > +{ > + return irqd->parent_data->hwirq; > +} > + > +static void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry, > + struct msi_desc *msi_desc) > +{ > + msi_entry->address =3D ((u64)msi_desc->msg.address_hi << 32) | > + msi_desc->msg.address_lo; > + msi_entry->data =3D msi_desc->msg.data; > +} > + > +static void hv_pci_vec_irq_domain_free(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs) > +{ > + struct hv_pci_chip_data *chip_data =3D domain->host_data; > + struct irq_data *irqd =3D irq_domain_get_irq_data(domain, virq); > + int first =3D irqd->hwirq - HV_PCI_MSI_SPI_START; > + > + mutex_lock(&chip_data->map_lock); > + bitmap_release_region(chip_data->spi_map, > + first, > + get_count_order(nr_irqs)); > + mutex_unlock(&chip_data->map_lock); > + irq_domain_reset_irq_data(irqd); > + irq_domain_free_irqs_parent(domain, virq, nr_irqs); > +} > + > +static int hv_pci_vec_alloc_device_irq(struct irq_domain *domain, > + unsigned int nr_irqs, > + irq_hw_number_t *hwirq) > +{ > + struct hv_pci_chip_data *chip_data =3D domain->host_data; > + unsigned int index; > + > + /* Find and allocate region from the SPI bitmap */ > + mutex_lock(&chip_data->map_lock); > + index =3D bitmap_find_free_region(chip_data->spi_map, > + HV_PCI_MSI_SPI_NR, > + get_count_order(nr_irqs)); > + mutex_unlock(&chip_data->map_lock); > + if (index < 0) > + return -ENOSPC; > + > + *hwirq =3D index + HV_PCI_MSI_SPI_START; > + > + return 0; > +} > + > +static int hv_pci_vec_irq_gic_domain_alloc(struct irq_domain *domain, > + unsigned int virq, > + irq_hw_number_t hwirq) > +{ > + struct irq_fwspec fwspec; > + > + fwspec.fwnode =3D domain->parent->fwnode; > + fwspec.param_count =3D 2; > + fwspec.param[0] =3D hwirq; > + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; > + > + return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); > +} > + > +static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs, > + void *args) > +{ > + irq_hw_number_t hwirq; > + unsigned int i; > + int ret; > + > + ret =3D hv_pci_vec_alloc_device_irq(domain, nr_irqs, &hwirq); > + if (ret) > + return ret; > + > + for (i =3D 0; i < nr_irqs; i++) { > + ret =3D hv_pci_vec_irq_gic_domain_alloc(domain, virq + i, > + hwirq + i); > + if (ret) > + goto free_irq; > + > + ret =3D irq_domain_set_hwirq_and_chip(domain, virq + i, > + hwirq + i, > + &hv_arm64_msi_irq_chip, > + domain->host_data); > + if (ret) > + goto free_irq; > + > + pr_debug("pID:%d vID:%u\n", (int)(hwirq + i), virq + i); > + } > + > + return 0; > + > +free_irq: > + hv_pci_vec_irq_domain_free(domain, virq, nr_irqs); > + > + return ret; > +} > + > +/* > + * Pick the first online cpu as the irq affinity that can be temporarily= used > + * for composing MSI from the hypervisor. GIC will eventually set the ri= ght > + * affinity for the irq and the 'unmask' will retarget the interrupt to = that > + * cpu. > + */ > +static int hv_pci_vec_irq_domain_activate(struct irq_domain *domain, > + struct irq_data *irqd, bool reserve) > +{ > + int cpu =3D cpumask_first(cpu_online_mask); > + > + irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); > + > + return 0; > +} > + > +static const struct irq_domain_ops hv_pci_domain_ops =3D { > + .alloc =3D hv_pci_vec_irq_domain_alloc, > + .free =3D hv_pci_vec_irq_domain_free, > + .activate =3D hv_pci_vec_irq_domain_activate, > +}; > + > +static int hv_pci_irqchip_init(void) > +{ > + static struct hv_pci_chip_data *chip_data; > + struct fwnode_handle *fn =3D NULL; > + int ret =3D -ENOMEM; > + > + chip_data =3D kzalloc(sizeof(*chip_data), GFP_KERNEL); > + if (!chip_data) > + return ret; > + > + mutex_init(&chip_data->map_lock); > + fn =3D irq_domain_alloc_named_fwnode("Hyper-V ARM64 vPCI"); > + if (!fn) > + goto free_chip; > + > + /* > + * IRQ domain once enabled, should not be removed since there is no > + * way to ensure that all the corresponding devices are also gone and > + * no interrupts will be generated. > + */ > + hv_msi_gic_irq_domain =3D acpi_irq_create_hierarchy(0, HV_PCI_MSI_SPI_N= R, > + fn, &hv_pci_domain_ops, > + chip_data); > + > + if (!hv_msi_gic_irq_domain) { > + pr_err("Failed to create Hyper-V ARMV vPCI MSI IRQ domain\n"); Typo in the above error message: "ARMV" should be "ARM64". > + goto free_chip; > + } > + > + return 0; > + > +free_chip: > + kfree(chip_data); > + if (fn) > + irq_domain_free_fwnode(fn); > + > + return ret; > +} > + > +static struct irq_domain *hv_pci_get_root_domain(void) > +{ > + return hv_msi_gic_irq_domain; > +} > +#endif //CONFIG_ARM64 Use "C" style comments. Michael