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* [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
@ 2021-07-16  6:33 Ani Sinha
  2021-07-16 13:25 ` Vitaly Kuznetsov
  0 siblings, 1 reply; 3+ messages in thread
From: Ani Sinha @ 2021-07-16  6:33 UTC (permalink / raw)
  To: linux-kernel
  Cc: anirban.sinha, mikelley, Ani Sinha, K. Y. Srinivasan,
	Haiyang Zhang, Stephen Hemminger, Wei Liu, Dexuan Cui,
	Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
	H. Peter Anvin, linux-hyperv

Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
of this synthetic MSR will allow hyper-v guests to report invariant TSC
CPU feature through CPUID. This comment adds this explanation to the code
and mentions where the Intel's generic platform init code reads this
feature bit from CPUID. The comment will help developers understand how
the two parts of the initialization (hyperV specific and non-hyperV
specific generic hw init) are related.

Signed-off-by: Ani Sinha <ani@anisinha.ca>
---
 arch/x86/kernel/cpu/mshyperv.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 715458b7729a..d2429748170d 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -368,6 +368,14 @@ static void __init ms_hyperv_init_platform(void)
 	machine_ops.crash_shutdown = hv_machine_crash_shutdown;
 #endif
 	if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
+		/*
+		 * Setting bit 0 of the synthetic MSR 0x40000118 enables
+		 * guests to report invariant TSC feature through CPUID
+		 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
+		 * early_init_intel() where this bit is examined. The
+		 * setting of this MSR bit should happen before init_intel()
+		 * is called.
+		 */
 		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
 		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 	}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
  2021-07-16  6:33 [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0 Ani Sinha
@ 2021-07-16 13:25 ` Vitaly Kuznetsov
  2021-07-16 13:33   ` Ani Sinha
  0 siblings, 1 reply; 3+ messages in thread
From: Vitaly Kuznetsov @ 2021-07-16 13:25 UTC (permalink / raw)
  To: Ani Sinha, linux-kernel
  Cc: anirban.sinha, mikelley, Ani Sinha, K. Y. Srinivasan,
	Haiyang Zhang, Stephen Hemminger, Wei Liu, Dexuan Cui,
	Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
	H. Peter Anvin, linux-hyperv

Ani Sinha <ani@anisinha.ca> writes:

> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
>
> Signed-off-by: Ani Sinha <ani@anisinha.ca>
> ---
>  arch/x86/kernel/cpu/mshyperv.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> index 715458b7729a..d2429748170d 100644
> --- a/arch/x86/kernel/cpu/mshyperv.c
> +++ b/arch/x86/kernel/cpu/mshyperv.c
> @@ -368,6 +368,14 @@ static void __init ms_hyperv_init_platform(void)
>  	machine_ops.crash_shutdown = hv_machine_crash_shutdown;
>  #endif
>  	if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
> +		/*
> +		 * Setting bit 0 of the synthetic MSR 0x40000118 enables
> +		 * guests to report invariant TSC feature through CPUID
> +		 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
> +		 * early_init_intel() where this bit is examined. The
> +		 * setting of this MSR bit should happen before init_intel()
> +		 * is called.

It should probably be emphasized, that write to 0x40000118
updates/changes guest visible CPUIDs. This may not be clear as CPUIDs
are generally considered 'static'. 

> +		 */
>  		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
>  		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
>  	}

-- 
Vitaly


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0
  2021-07-16 13:25 ` Vitaly Kuznetsov
@ 2021-07-16 13:33   ` Ani Sinha
  0 siblings, 0 replies; 3+ messages in thread
From: Ani Sinha @ 2021-07-16 13:33 UTC (permalink / raw)
  To: Vitaly Kuznetsov
  Cc: Ani Sinha, linux-kernel, anirban.sinha, mikelley,
	K. Y. Srinivasan, Haiyang Zhang, Stephen Hemminger, Wei Liu,
	Dexuan Cui, Thomas Gleixner, Ingo Molnar, Borislav Petkov, x86,
	H. Peter Anvin, linux-hyperv



On Fri, 16 Jul 2021, Vitaly Kuznetsov wrote:

> Ani Sinha <ani@anisinha.ca> writes:
>
> > Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> > added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> > of this synthetic MSR will allow hyper-v guests to report invariant TSC
> > CPU feature through CPUID. This comment adds this explanation to the code
> > and mentions where the Intel's generic platform init code reads this
> > feature bit from CPUID. The comment will help developers understand how
> > the two parts of the initialization (hyperV specific and non-hyperV
> > specific generic hw init) are related.
> >
> > Signed-off-by: Ani Sinha <ani@anisinha.ca>
> > ---
> >  arch/x86/kernel/cpu/mshyperv.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> > index 715458b7729a..d2429748170d 100644
> > --- a/arch/x86/kernel/cpu/mshyperv.c
> > +++ b/arch/x86/kernel/cpu/mshyperv.c
> > @@ -368,6 +368,14 @@ static void __init ms_hyperv_init_platform(void)
> >  	machine_ops.crash_shutdown = hv_machine_crash_shutdown;
> >  #endif
> >  	if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
> > +		/*
> > +		 * Setting bit 0 of the synthetic MSR 0x40000118 enables
> > +		 * guests to report invariant TSC feature through CPUID
> > +		 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
> > +		 * early_init_intel() where this bit is examined. The
> > +		 * setting of this MSR bit should happen before init_intel()
> > +		 * is called.
>
> It should probably be emphasized, that write to 0x40000118
> updates/changes guest visible CPUIDs. This may not be clear as CPUIDs
> are generally considered 'static'.

Patch v2 sent.


^ permalink raw reply	[flat|nested] 3+ messages in thread

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2021-07-16  6:33 [PATCH] x86/hyperv: add comment describing TSC_INVARIANT_CONTROL MSR setting bit 0 Ani Sinha
2021-07-16 13:25 ` Vitaly Kuznetsov
2021-07-16 13:33   ` Ani Sinha

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