From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7468AC2D0A3 for ; Sat, 24 Oct 2020 08:26:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC07D223EA for ; Sat, 24 Oct 2020 08:26:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="j8/f7zSF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760049AbgJXI0Z (ORCPT ); Sat, 24 Oct 2020 04:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759993AbgJXI0X (ORCPT ); Sat, 24 Oct 2020 04:26:23 -0400 Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28B26C0613CE; Sat, 24 Oct 2020 01:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=Mime-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=QMDrw5Rd1WyYd+89WQH0nJz4+3+13jSc3foFQHRzoaY=; b=j8/f7zSFKdXWKs8hiYMkcyTJ5t CkDz0EmOYrQCUYAT/ZOGdFOgRmFsDbmoBWxCLlOQx5da1hrAiktjSrrk3RHqdEVCZ0ju/VyYJc7Yo 68brl+Eok/SaB1Q4FviYYWgSYStKvP57kZATPuDBU9zOM6PSXi3RqVw/ymSjlNm35yfnJ/Cln9wev iGmFAD8OR0fJ1KSlmH6TKDvmpxkYpngsv9xf3TS+Gm/KSL4qFWx2G4M3OfxE/iCMDaPPXrHuEmwXM MJYuZWOZhEJ7boNXLN/C3D/5wjXQ3rzybU4s7oc4jQh3hQnQ4T8om7eqldsvqL5OW3/u5KJRM/mbD qBHOIGnw==; Received: from [54.239.6.185] (helo=freeip.amazon.com) by merlin.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kWEsR-00038o-KI; Sat, 24 Oct 2020 08:26:16 +0000 Message-ID: Subject: Re: [PATCH v2 8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message From: David Woodhouse To: Thomas Gleixner , x86@kernel.org Cc: kvm , Paolo Bonzini , linux-kernel , linux-hyperv@vger.kernel.org, Dexuan Cui Date: Sat, 24 Oct 2020 09:26:13 +0100 In-Reply-To: <87d01863a2.fsf@nanos.tec.linutronix.de> References: <87y2jy542v.fsf@nanos.tec.linutronix.de> <87d01863a2.fsf@nanos.tec.linutronix.de> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-mUO5fenvrU340O1S27vI" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Mime-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by merlin.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org Archived-At: List-Archive: List-Post: --=-mUO5fenvrU340O1S27vI Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2020-10-23 at 23:28 +0200, Thomas Gleixner wrote: > On Fri, Oct 23 2020 at 11:10, David Woodhouse wrote: > > On 22 October 2020 22:43:52 BST, Thomas Gleixner w= rote: > > It makes the callers slightly more readable, not having to cast to uint= 32_t* from the struct. > >=20 > > I did ponder defining a new struct with bitfields named along the > > lines of 'msi_addr_bits_19_to_4', but that seemed like overkill. >=20 > I did something like this in the meantime, because all of this just > sucks. >=20 > git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git x86/apic >=20 > Hot of the press and completely untested. Hm, your struct IO_APIC_route_entry isn't actually a union; you've defined a 128-bit structure with the IR fields *following* the non-IR fields. But there *is* a union in io_apic.c, of that 128-bit structure and two uint32_ts. Suspect that wasn't quite what you intended. I'll prod at it this morning and turn it into a single union of the three, and give it some testing. Also, my "Move MSI support into hpet.c" patch=C2=B9 got updated to s/CONFIG_PCI_MSI/CONFIG_GENERIC_MSI_IRQ/ at about line 53 for the MSI- related variable declarations, which was going to be in the next version I posted. I was also hoping Paolo was going to take the patch which just defines the KVM_FEATURE_MSI_EXT_DEST_ID bit=C2=B2 ASAP, so that we end up with a second patch=C2=B3 that *just* wires it up to x86_init.msi_ext_dest_id() fo= r KVM. =C2=B9 https://git.infradead.org/users/dwmw2/linux.git/commitdiff/734719c1f= 4 =C2=B2 https://git.infradead.org/users/dwmw2/linux.git/commitdiff/3f371d674= 9 =C2=B3 https://git.infradead.org/users/dwmw2/linux.git/commitdiff/8399e14eb= 5 > Yes, we can't avoid the bit swizzling at all. But it can be made more > readable. Hm, I was about to concede that your version is a bit more readable. But then I got to your new __ipi_msi_compose_msg() and realised that it isn't working because it's setting the 0xFEE base address in the _low_ bits, somehow... msg->arch_addr_lo.base_address =3D X86_MSI_BASE_ADDRESS_LOW; printk("1 Compose MSI message %x/%x\n", msg->address_lo, msg->data); msg->arch_addr_lo.dest_mode_logical =3D apic->dest_mode_logical; printk("2 Compose MSI message %x/%x\n", msg->address_lo, msg->data); msg->arch_addr_lo.destid_0_7 =3D cfg->dest_apicid & 0xFF; printk("3 Compose MSI message %x/%x\n", msg->address_lo, msg->data); [ 1.793874] 1 Compose MSI message fee/0 [ 1.794310] 2 Compose MSI message fee/0 [ 1.794768] 3 Compose MSI message f02/0 And now I wish it was just a simple shift instead of an unholy maze of overlapping unions of bitfields. But I'll make more coffee and stare at it harder... > Yes, that code is horrid, but adding a comment to that effect when > changing it is not asked too much, right? Sure. I just actually hadn't noticed that setting the dest/vector bits right there was entirely redundant in the first place. > I'm still wrapping my head around getting rid of this thing completely > because now it's just a subset of your KVM case with the only > restriction that I/O-APIC cannot be affined to any CPU with a APIC id > greater than 255. It was only ever that restriction anyway, wasn't it? Hyper-V PCI has its own MSI handling, and there's no HPET so it was only ever the I/OAPIC which was problematic there. There are Hyper-V VM sizes with 416 vCPUs which depend on this today, and which don't have the 15-bit MSI extension. Removing hyperv-iommu would prevent us from using all the vCPUs on those. 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