From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DDB4C4332F for ; Tue, 22 Nov 2022 18:30:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234264AbiKVSar (ORCPT ); Tue, 22 Nov 2022 13:30:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231766AbiKVSaq (ORCPT ); Tue, 22 Nov 2022 13:30:46 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63DA57FF21; Tue, 22 Nov 2022 10:30:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669141846; x=1700677846; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=BEn7669Y/qpoLWxlJH/t+9MokSfp1qnFTNQyr2DK8ug=; b=XUh1G8AgEfrrR0AmQdgO16MuacflTVvpBN+U4N7BAkxySmgrfZpbmGhA 0LnUlcfbdHSdTIeHtbW2IzgLFYuwiUFB4qL42GWpBYRkLLBNVUFmODvlA PIcQFP7g3JVCr1rEZ7APc5KeXUV2pMXL1iQPh8JOJeilGMDy+BB1gDawk r/DlLbtuLh3oAWuscR5ZRom0S0XMMENqDRJxdY9ztF6SZqHAT5zDHk9CF m8/di5+ej8wi6g3LZbhhDDq8YWUKyv0rBAs+38xdNoTBbGnn68yE7TUlJ 7cPbsySsazqp7YOlbXpw9QnOKPpsds3Em5Mde+ayOhY1bA2ZCPy8ynDqc g==; X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="340757644" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="340757644" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 10:30:32 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="783936620" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="783936620" Received: from coltsavx-mobl1.amr.corp.intel.com (HELO [10.255.0.114]) ([10.255.0.114]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 10:30:25 -0800 Message-ID: Date: Tue, 22 Nov 2022 10:30:23 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [Patch v3 07/14] x86/hyperv: Change vTOM handling to use standard coco mechanisms Content-Language: en-US To: "Michael Kelley (LINUX)" , Borislav Petkov Cc: "hpa@zytor.com" , KY Srinivasan , Haiyang Zhang , "wei.liu@kernel.org" , Dexuan Cui , "luto@kernel.org" , "peterz@infradead.org" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "lpieralisi@kernel.org" , "robh@kernel.org" , "kw@linux.com" , "bhelgaas@google.com" , "arnd@arndb.de" , "hch@infradead.org" , "m.szyprowski@samsung.com" , "robin.murphy@arm.com" , "thomas.lendacky@amd.com" , "brijesh.singh@amd.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "dave.hansen@linux.intel.com" , Tianyu Lan , "kirill.shutemov@linux.intel.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "ak@linux.intel.com" , "isaku.yamahata@intel.com" , "Williams, Dan J" , "jane.chu@oracle.com" , "seanjc@google.com" , "tony.luck@intel.com" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-hyperv@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-arch@vger.kernel.org" , "iommu@lists.linux.dev" References: <1668624097-14884-1-git-send-email-mikelley@microsoft.com> <1668624097-14884-8-git-send-email-mikelley@microsoft.com> From: Dave Hansen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-hyperv@vger.kernel.org On 11/22/22 10:22, Michael Kelley (LINUX) wrote: > Anyway, that's where I think this should go. Does it make sense? > Other thoughts? I think hard-coding the C-bit behavior and/or position to a vendor was probably a bad idea. Even the comment: u64 cc_mkenc(u64 val) { /* * Both AMD and Intel use a bit in the page table to indicate * encryption status of the page. * * - for AMD, bit *set* means the page is encrypted * - for Intel *clear* means encrypted. */ doesn't make a lot of sense now. Maybe we should just have a: CC_ATTR_ENC_SET which gets set for the "AMD" behavior and is clear for the "Intel" behavior. Hyper-V code running on AMD can set the attribute to get teh "Intel" behavior. That sure beats having a Hyper-V vendor.