* [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver
2020-07-22 12:31 [PATCH 0/4] add i2c support for mt8192 Qii Wang
@ 2020-07-22 12:31 ` Qii Wang
2020-07-22 15:26 ` Matthias Brugger
2020-07-23 1:29 ` Yingjoe Chen
2020-07-22 12:31 ` [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits Qii Wang
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-22 12:31 UTC (permalink / raw)
To: wsa
Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, leilk.liu, qii.wang,
qiangming.xia
With the apdma remove hand-shake signal, it need to keep i2c and
apdma in sync manually.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index deef69e..e6b984a 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -48,6 +48,9 @@
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_ASYNC_MODE 0x0004
+#define I2C_DMA_SKIP_CONFIG 0x0010
+#define I2C_DMA_DIR_CHANGE 0x0200
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x0000
#define I2C_DMA_CLR_FLAG 0x0000
@@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
unsigned char timing_adjust: 1;
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
+ unsigned char apdma_sync: 1;
};
struct mtk_i2c_ac_timing {
@@ -311,6 +315,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -324,6 +329,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -337,6 +343,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -350,6 +357,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -362,6 +370,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -375,6 +384,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
+ .apdma_sync = 0,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 start_reg;
u16 control_reg;
u16 restart_flag = 0;
+ u16 dma_sync = 0;
u32 reg_4g_mode;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
@@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
}
+ if (i2c->dev_comp->apdma_sync) {
+ dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
+ if (i2c->op == I2C_MASTER_WRRD)
+ dma_sync |= I2C_DMA_DIR_CHANGE;
+ }
+
/* Prepare buffer data to start transfer */
if (i2c->op == I2C_MASTER_RD) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_rd_buf)
@@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
} else if (i2c->op == I2C_MASTER_WR) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
@@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
} else {
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver
2020-07-22 12:31 ` [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
@ 2020-07-22 15:26 ` Matthias Brugger
2020-07-23 1:29 ` Yingjoe Chen
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Brugger @ 2020-07-22 15:26 UTC (permalink / raw)
To: Qii Wang, wsa
Cc: qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On 22/07/2020 14:31, Qii Wang wrote:
> With the apdma remove hand-shake signal, it need to keep i2c and
> apdma in sync manually.
>
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
> 1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index deef69e..e6b984a 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -48,6 +48,9 @@
>
> #define I2C_DMA_CON_TX 0x0000
> #define I2C_DMA_CON_RX 0x0001
> +#define I2C_DMA_ASYNC_MODE 0x0004
> +#define I2C_DMA_SKIP_CONFIG 0x0010
> +#define I2C_DMA_DIR_CHANGE 0x0200
> #define I2C_DMA_START_EN 0x0001
> #define I2C_DMA_INT_FLAG_NONE 0x0000
> #define I2C_DMA_CLR_FLAG 0x0000
> @@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
> unsigned char timing_adjust: 1;
> unsigned char dma_sync: 1;
> unsigned char ltiming_adjust: 1;
> + unsigned char apdma_sync: 1;
> };
>
> struct mtk_i2c_ac_timing {
> @@ -311,6 +315,7 @@ struct i2c_spec_values {
> .timing_adjust = 1,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -324,6 +329,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -337,6 +343,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -350,6 +357,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -362,6 +370,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8183_compat = {
> @@ -375,6 +384,7 @@ struct i2c_spec_values {
> .timing_adjust = 1,
> .dma_sync = 1,
> .ltiming_adjust = 1,
> + .apdma_sync = 0,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> u16 start_reg;
> u16 control_reg;
> u16 restart_flag = 0;
> + u16 dma_sync = 0;
> u32 reg_4g_mode;
> u8 *dma_rd_buf = NULL;
> u8 *dma_wr_buf = NULL;
> @@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
> }
>
> + if (i2c->dev_comp->apdma_sync) {
> + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
> + if (i2c->op == I2C_MASTER_WRRD)
> + dma_sync |= I2C_DMA_DIR_CHANGE;
> + }
> +
> /* Prepare buffer data to start transfer */
> if (i2c->op == I2C_MASTER_RD) {
> writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_rd_buf)
> @@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
> } else if (i2c->op == I2C_MASTER_WR) {
> writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_wr_buf)
> @@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
> } else {
> writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_wr_buf)
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver
2020-07-22 12:31 ` [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
2020-07-22 15:26 ` Matthias Brugger
@ 2020-07-23 1:29 ` Yingjoe Chen
2020-07-23 6:01 ` Qii Wang
1 sibling, 1 reply; 13+ messages in thread
From: Yingjoe Chen @ 2020-07-23 1:29 UTC (permalink / raw)
To: Qii Wang
Cc: wsa, qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On Wed, 2020-07-22 at 20:31 +0800, Qii Wang wrote:
> With the apdma remove hand-shake signal, it need to keep i2c and
> apdma in sync manually.
>
Looks good to me,
Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Just a reminder, we have another patch 'i2c: mediatek: Add to support
continuous mode' under review now. Please remember to update OFFSET_CON
access code in that patch.
Joe.C
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
> 1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index deef69e..e6b984a 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -48,6 +48,9 @@
>
> #define I2C_DMA_CON_TX 0x0000
> #define I2C_DMA_CON_RX 0x0001
> +#define I2C_DMA_ASYNC_MODE 0x0004
> +#define I2C_DMA_SKIP_CONFIG 0x0010
> +#define I2C_DMA_DIR_CHANGE 0x0200
> #define I2C_DMA_START_EN 0x0001
> #define I2C_DMA_INT_FLAG_NONE 0x0000
> #define I2C_DMA_CLR_FLAG 0x0000
> @@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
> unsigned char timing_adjust: 1;
> unsigned char dma_sync: 1;
> unsigned char ltiming_adjust: 1;
> + unsigned char apdma_sync: 1;
> };
>
> struct mtk_i2c_ac_timing {
> @@ -311,6 +315,7 @@ struct i2c_spec_values {
> .timing_adjust = 1,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -324,6 +329,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -337,6 +343,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -350,6 +357,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -362,6 +370,7 @@ struct i2c_spec_values {
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> + .apdma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8183_compat = {
> @@ -375,6 +384,7 @@ struct i2c_spec_values {
> .timing_adjust = 1,
> .dma_sync = 1,
> .ltiming_adjust = 1,
> + .apdma_sync = 0,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> u16 start_reg;
> u16 control_reg;
> u16 restart_flag = 0;
> + u16 dma_sync = 0;
> u32 reg_4g_mode;
> u8 *dma_rd_buf = NULL;
> u8 *dma_wr_buf = NULL;
> @@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
> }
>
> + if (i2c->dev_comp->apdma_sync) {
> + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
> + if (i2c->op == I2C_MASTER_WRRD)
> + dma_sync |= I2C_DMA_DIR_CHANGE;
> + }
> +
> /* Prepare buffer data to start transfer */
> if (i2c->op == I2C_MASTER_RD) {
> writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_rd_buf)
> @@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
> } else if (i2c->op == I2C_MASTER_WR) {
> writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_wr_buf)
> @@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
> } else {
> writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
> - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
> + writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
>
> dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> if (!dma_wr_buf)
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver
2020-07-23 1:29 ` Yingjoe Chen
@ 2020-07-23 6:01 ` Qii Wang
0 siblings, 0 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-23 6:01 UTC (permalink / raw)
To: Yingjoe Chen
Cc: wsa, qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On Thu, 2020-07-23 at 09:29 +0800, Yingjoe Chen wrote:
> On Wed, 2020-07-22 at 20:31 +0800, Qii Wang wrote:
> > With the apdma remove hand-shake signal, it need to keep i2c and
> > apdma in sync manually.
> >
>
> Looks good to me,
>
> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
>
>
> Just a reminder, we have another patch 'i2c: mediatek: Add to support
> continuous mode' under review now. Please remember to update OFFSET_CON
> access code in that patch.
>
> Joe.C
>
>
I and Qiangming are looking at whether the original multi-write code can
cover it, After confirming again, then we will decide whether it need to
send that patch. Thanks for your comments.
>
> > Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
> > 1 file changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index deef69e..e6b984a 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -48,6 +48,9 @@
> >
> > #define I2C_DMA_CON_TX 0x0000
> > #define I2C_DMA_CON_RX 0x0001
> > +#define I2C_DMA_ASYNC_MODE 0x0004
> > +#define I2C_DMA_SKIP_CONFIG 0x0010
> > +#define I2C_DMA_DIR_CHANGE 0x0200
> > #define I2C_DMA_START_EN 0x0001
> > #define I2C_DMA_INT_FLAG_NONE 0x0000
> > #define I2C_DMA_CLR_FLAG 0x0000
> > @@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
> > unsigned char timing_adjust: 1;
> > unsigned char dma_sync: 1;
> > unsigned char ltiming_adjust: 1;
> > + unsigned char apdma_sync: 1;
> > };
> >
> > struct mtk_i2c_ac_timing {
> > @@ -311,6 +315,7 @@ struct i2c_spec_values {
> > .timing_adjust = 1,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -324,6 +329,7 @@ struct i2c_spec_values {
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -337,6 +343,7 @@ struct i2c_spec_values {
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -350,6 +357,7 @@ struct i2c_spec_values {
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -362,6 +370,7 @@ struct i2c_spec_values {
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt8183_compat = {
> > @@ -375,6 +384,7 @@ struct i2c_spec_values {
> > .timing_adjust = 1,
> > .dma_sync = 1,
> > .ltiming_adjust = 1,
> > + .apdma_sync = 0,
> > };
> >
> > static const struct of_device_id mtk_i2c_of_match[] = {
> > @@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > u16 start_reg;
> > u16 control_reg;
> > u16 restart_flag = 0;
> > + u16 dma_sync = 0;
> > u32 reg_4g_mode;
> > u8 *dma_rd_buf = NULL;
> > u8 *dma_wr_buf = NULL;
> > @@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
> > }
> >
> > + if (i2c->dev_comp->apdma_sync) {
> > + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
> > + if (i2c->op == I2C_MASTER_WRRD)
> > + dma_sync |= I2C_DMA_DIR_CHANGE;
> > + }
> > +
> > /* Prepare buffer data to start transfer */
> > if (i2c->op == I2C_MASTER_RD) {
> > writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> > - writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
> > + writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
> >
> > dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> > if (!dma_rd_buf)
> > @@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
> > } else if (i2c->op == I2C_MASTER_WR) {
> > writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
> > - writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
> > + writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
> >
> > dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> > if (!dma_wr_buf)
> > @@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
> > } else {
> > writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
> > - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
> > + writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
> >
> > dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
> > if (!dma_wr_buf)
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
2020-07-22 12:31 [PATCH 0/4] add i2c support for mt8192 Qii Wang
2020-07-22 12:31 ` [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
@ 2020-07-22 12:31 ` Qii Wang
2020-07-22 15:38 ` Matthias Brugger
2020-07-23 1:24 ` Yingjoe Chen
2020-07-22 12:31 ` [PATCH 3/4] dt-bindings: i2c: update bindings for MT8192 SoC Qii Wang
2020-07-22 12:31 ` [PATCH 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192 Qii Wang
3 siblings, 2 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-22 12:31 UTC (permalink / raw)
To: wsa
Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, leilk.liu, qii.wang,
qiangming.xia
Replace 'support_33bits with 'dma_max_support' for DMA mask
operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e6b984a..e475877 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
unsigned char apdma_sync: 1;
+ unsigned char max_dma_support;
};
struct mtk_i2c_ac_timing {
@@ -311,11 +312,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -325,11 +326,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -339,11 +340,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -353,11 +354,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -366,11 +367,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -380,11 +381,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -796,11 +797,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
return 0;
}
-static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
-{
- return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
-}
-
static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
int num, int left_num)
{
@@ -885,8 +881,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -908,8 +904,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
}
@@ -954,11 +950,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -1232,8 +1228,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (i2c->dev_comp->support_33bits) {
- ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
+ if (i2c->dev_comp->max_dma_support > 32) {
+ ret = dma_set_mask(&pdev->dev,
+ DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
if (ret) {
dev_err(&pdev->dev, "dma_set_mask return error.\n");
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
2020-07-22 12:31 ` [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits Qii Wang
@ 2020-07-22 15:38 ` Matthias Brugger
2020-07-23 5:47 ` Qii Wang
2020-07-23 1:24 ` Yingjoe Chen
1 sibling, 1 reply; 13+ messages in thread
From: Matthias Brugger @ 2020-07-22 15:38 UTC (permalink / raw)
To: Qii Wang, wsa
Cc: qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On 22/07/2020 14:31, Qii Wang wrote:
> Replace 'support_33bits with 'dma_max_support' for DMA mask
> operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.
Please explain more in detail what you are doing and how this fits to the way
the HW works.
>
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
> 1 file changed, 17 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index e6b984a..e475877 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
> unsigned char dma_sync: 1;
> unsigned char ltiming_adjust: 1;
> unsigned char apdma_sync: 1;
> + unsigned char max_dma_support;
> };
>
> struct mtk_i2c_ac_timing {
> @@ -311,11 +312,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 1,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -325,11 +326,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 0,
> .aux_len_reg = 0,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -339,11 +340,11 @@ struct i2c_spec_values {
> .dcm = 0,
> .auto_restart = 0,
> .aux_len_reg = 0,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -353,11 +354,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -366,11 +367,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct mtk_i2c_compatible mt8183_compat = {
> @@ -380,11 +381,11 @@ struct i2c_spec_values {
> .dcm = 0,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 1,
> .dma_sync = 1,
> .ltiming_adjust = 1,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -796,11 +797,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> return 0;
> }
>
> -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> -{
> - return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
I2C_DMA_4G_MODE define could now be deleted as well.
Regards,
Matthias
> -}
> -
> static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> int num, int left_num)
> {
> @@ -885,8 +881,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(rpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> }
>
> @@ -908,8 +904,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(wpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> }
>
> @@ -954,11 +950,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(wpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
>
> - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> + reg_4g_mode = upper_32_bits(rpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> }
>
> @@ -1232,8 +1228,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
> + if (i2c->dev_comp->max_dma_support > 32) {
> + ret = dma_set_mask(&pdev->dev,
> + DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
> if (ret) {
> dev_err(&pdev->dev, "dma_set_mask return error.\n");
> return ret;
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
2020-07-22 15:38 ` Matthias Brugger
@ 2020-07-23 5:47 ` Qii Wang
0 siblings, 0 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-23 5:47 UTC (permalink / raw)
To: Matthias Brugger
Cc: wsa, qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On Wed, 2020-07-22 at 17:38 +0200, Matthias Brugger wrote:
>
> On 22/07/2020 14:31, Qii Wang wrote:
> > Replace 'support_33bits with 'dma_max_support' for DMA mask
> > operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.
>
> Please explain more in detail what you are doing and how this fits to the way
> the HW works.
>
As Yingjoe sir said, Newer MTK chip support more than 8GB of dram, and
the register TX/RX_4G_MODE of APDMA has added corresponding bit to
support.So we Replace support_33bits with more general dma_max_support.I
will modify the title and commit as :
i2c: mediatek: Add access to more than 8GB dram in i2c driver
Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support and remove mtk_i2c_set_4g_mode.
> >
> > Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
> > 1 file changed, 17 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index e6b984a..e475877 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
> > unsigned char dma_sync: 1;
> > unsigned char ltiming_adjust: 1;
> > unsigned char apdma_sync: 1;
> > + unsigned char max_dma_support;
> > };
> >
> > struct mtk_i2c_ac_timing {
> > @@ -311,11 +312,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 1,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -325,11 +326,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 0,
> > .aux_len_reg = 0,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -339,11 +340,11 @@ struct i2c_spec_values {
> > .dcm = 0,
> > .auto_restart = 0,
> > .aux_len_reg = 0,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -353,11 +354,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -366,11 +367,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct mtk_i2c_compatible mt8183_compat = {
> > @@ -380,11 +381,11 @@ struct i2c_spec_values {
> > .dcm = 0,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 1,
> > .dma_sync = 1,
> > .ltiming_adjust = 1,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct of_device_id mtk_i2c_of_match[] = {
> > @@ -796,11 +797,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> > return 0;
> > }
> >
> > -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> > -{
> > - return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
>
> I2C_DMA_4G_MODE define could now be deleted as well.
>
> Regards,
> Matthias
>
> > -}
> > -
> > static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > int num, int left_num)
> > {
> > @@ -885,8 +881,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(rpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> > }
> >
> > @@ -908,8 +904,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(wpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> > }
> >
> > @@ -954,11 +950,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(wpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> >
> > - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> > + reg_4g_mode = upper_32_bits(rpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> > }
> >
> > @@ -1232,8 +1228,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> > return -EINVAL;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + ret = dma_set_mask(&pdev->dev,
> > + DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
> > if (ret) {
> > dev_err(&pdev->dev, "dma_set_mask return error.\n");
> > return ret;
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
2020-07-22 12:31 ` [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits Qii Wang
2020-07-22 15:38 ` Matthias Brugger
@ 2020-07-23 1:24 ` Yingjoe Chen
2020-07-23 6:03 ` Qii Wang
1 sibling, 1 reply; 13+ messages in thread
From: Yingjoe Chen @ 2020-07-23 1:24 UTC (permalink / raw)
To: Qii Wang
Cc: wsa, qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On Wed, 2020-07-22 at 20:31 +0800, Qii Wang wrote:
> Replace 'support_33bits with 'dma_max_support' for DMA mask
> operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.
This doesn't explain why we need this patch. How about:
Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support.
>
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
> 1 file changed, 17 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index e6b984a..e475877 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
> unsigned char dma_sync: 1;
> unsigned char ltiming_adjust: 1;
> unsigned char apdma_sync: 1;
> + unsigned char max_dma_support;
support_33bits is no longer used. Please remove it.
Joe.C
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits
2020-07-23 1:24 ` Yingjoe Chen
@ 2020-07-23 6:03 ` Qii Wang
0 siblings, 0 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-23 6:03 UTC (permalink / raw)
To: Yingjoe Chen
Cc: wsa, qiangming.xia, devicetree, srv_heupstream, leilk.liu,
linux-kernel, robh+dt, linux-mediatek, linux-i2c,
linux-arm-kernel
On Thu, 2020-07-23 at 09:24 +0800, Yingjoe Chen wrote:
> On Wed, 2020-07-22 at 20:31 +0800, Qii Wang wrote:
> > Replace 'support_33bits with 'dma_max_support' for DMA mask
> > operation, and replace 'mtk_i2c_set_4g_mode' with 'upper_32_bits'.
>
> This doesn't explain why we need this patch. How about:
>
> Newer MTK chip support more than 8GB of dram. Replace support_33bits
> with more general dma_max_support.
>
ok, Thanks for your comments.
>
> >
> > Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 37 +++++++++++++++++--------------------
> > 1 file changed, 17 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index e6b984a..e475877 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -209,6 +209,7 @@ struct mtk_i2c_compatible {
> > unsigned char dma_sync: 1;
> > unsigned char ltiming_adjust: 1;
> > unsigned char apdma_sync: 1;
> > + unsigned char max_dma_support;
>
> support_33bits is no longer used. Please remove it.
>
> Joe.C
>
ok.
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] dt-bindings: i2c: update bindings for MT8192 SoC
2020-07-22 12:31 [PATCH 0/4] add i2c support for mt8192 Qii Wang
2020-07-22 12:31 ` [PATCH 1/4] i2c: mediatek: Add apdma sync in i2c driver Qii Wang
2020-07-22 12:31 ` [PATCH 2/4] i2c: mediatek: Support DMA mask range over 33-bits Qii Wang
@ 2020-07-22 12:31 ` Qii Wang
2020-07-23 21:18 ` Rob Herring
2020-07-22 12:31 ` [PATCH 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192 Qii Wang
3 siblings, 1 reply; 13+ messages in thread
From: Qii Wang @ 2020-07-22 12:31 UTC (permalink / raw)
To: wsa
Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, leilk.liu, qii.wang,
qiangming.xia
Add a DT binding documentation for the MT8192 soc.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
index 88b71c1..7f0194f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
@@ -14,6 +14,7 @@ Required properties:
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] dt-bindings: i2c: update bindings for MT8192 SoC
2020-07-22 12:31 ` [PATCH 3/4] dt-bindings: i2c: update bindings for MT8192 SoC Qii Wang
@ 2020-07-23 21:18 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-07-23 21:18 UTC (permalink / raw)
To: Qii Wang
Cc: qiangming.xia, linux-kernel, devicetree, wsa, linux-arm-kernel,
leilk.liu, linux-i2c, robh+dt, linux-mediatek, srv_heupstream
On Wed, 22 Jul 2020 20:31:45 +0800, Qii Wang wrote:
> Add a DT binding documentation for the MT8192 soc.
>
> Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] i2c: mediatek: Add i2c compatible for MediaTek MT8192
2020-07-22 12:31 [PATCH 0/4] add i2c support for mt8192 Qii Wang
` (2 preceding siblings ...)
2020-07-22 12:31 ` [PATCH 3/4] dt-bindings: i2c: update bindings for MT8192 SoC Qii Wang
@ 2020-07-22 12:31 ` Qii Wang
3 siblings, 0 replies; 13+ messages in thread
From: Qii Wang @ 2020-07-22 12:31 UTC (permalink / raw)
To: wsa
Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel,
linux-mediatek, srv_heupstream, leilk.liu, qii.wang,
qiangming.xia
Add i2c compatible for MT8192. Compare to MT8183 i2c controller,
MT8192 support more then 8GB DMA mode.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e475877..47f3eef 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -388,6 +388,20 @@ struct i2c_spec_values {
.max_dma_support = 33,
};
+static const struct mtk_i2c_compatible mt8192_compat = {
+ .quirks = &mt8183_i2c_quirks,
+ .regs = mt_i2c_regs_v2,
+ .pmic_i2c = 0,
+ .dcm = 0,
+ .auto_restart = 1,
+ .aux_len_reg = 1,
+ .timing_adjust = 1,
+ .dma_sync = 1,
+ .ltiming_adjust = 1,
+ .apdma_sync = 1,
+ .max_dma_support = 36,
+};
+
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
@@ -395,6 +409,7 @@ struct i2c_spec_values {
{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
+ { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread